reg16.vhd

出租车计费器,VHDL实现

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  reg16  IS
    PORT(
         clk,clr:IN STD_LOGIC;
               d:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
               q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END  reg16;

ARCHITECTURE  execute  OF  reg16  IS
  SIGNAL  r16s:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
      PROCESS(clk,clr)
      BEGIN
           IF clr='1'THEN
           r16s<="0000000000000000";
           ELSIF  clk'EVENT AND clk='1'THEN
           r16s(6 DOWNTO 0)<=r16s(7 DOWNTO 1);
           r16s(15 DOWNTO 7)<=d;
           END IF;
      END PROCESS;
   q<=r16s;
END  execute;