count60.vhd

出租车计费器,VHDL实现

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;
entity  count60 is
port(
     clk,clr,start:in  std_logic;
     min:out  std_logic_vector(5 downto 0);
     hor:out  std_logic     
    );
end  count60;
architecture func of count60 is
signal  min_tmp:std_logic_vector(5 downto 0);
begin
      process(clk)
      begin
       if clr='1'then
         min_tmp<="000000";
       else  
        if(clk'event and clk='1') then 
         if start='0'then
          if(min_tmp ="111011") then
              min_tmp<="000000";
          else
              min_tmp<=min_tmp+1; 
           end if;
         end if;
        end if;
        end if; 
       end process;
process(min_tmp)
begin
  if min_tmp ="111011"then hor<='1';
  else    hor<='0';
  end  if;
end   process;         
  min<=min_tmp;
end func;