hedfile.vhd

出租车计费器,VHDL实现

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY hedfile IS
    PORT(
           clk,clr,start,quiclk:IN STD_LOGIC;
           strpri:IN STD_LOGIC_VECTOR(3  DOWNTO  0);
        speed,unipri:IN STD_LOGIC_VECTOR(1  DOWNTO  0);
                wei8,dist1:OUT std_logic_vector(7 DOWNTO 0);
                 seg:OUT STD_LOGIC_VECTOR(6 DOWNTO  0));
END  hedfile;

ARCHITECTURE  execute  OF hedfile  IS
    COMPONENT  count60
         port(
     clk,clr,start:in  std_logic;
     min:out  std_logic_vector(5 downto 0);
     hor:out  std_logic);
    END COMPONENT;
    COMPONENT  multi8
          PORT(
         clk,start:IN STD_LOGIC;
              a,b :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
           multend:OUT STD_LOGIC;
              dout:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
    END COMPONENT;
    COMPONENT  add8
          PORT(
           cin:IN STD_LOGIC;
          a,b :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            s :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          cout:OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT  decoder3_8
          port(
     quiclk:in  std_logic;
     wei8:out std_logic_vector(7 downto 0)
    );
    END COMPONENT;
    COMPONENT  duanxuan
       PORT(
           wei8,strpri,fare,sec,min:IN STD_LOGIC_VECTOR(7  DOWNTO  0);
            unipri:IN STD_LOGIC_VECTOR(1  DOWNTO  0);     
             start:IN STD_LOGIC;
               seg:OUT STD_LOGIC_VECTOR(6 DOWNTO  0)); 
    END COMPONENT;
    COMPONENT changebcd
       PORT(  
       dat:IN STD_LOGIC_VECTOR(6  DOWNTO  0);
       bcd:OUT STD_LOGIC_VECTOR(7  DOWNTO  0));
    END COMPONENT;
    
    SIGNAL  hor_temp,start_temp,multi_temp,cout_temp,cin_temp,flag10_temp,temp:STD_LOGIC;
	SIGNAL  min,sec:STD_LOGIC_VECTOR(5  DOWNTO  0); 
	SIGNAL  dist,fare1: STD_LOGIC_VECTOR(15  DOWNTO  0); 
	SIGNAL  wei8_temp,fare2,strpri_temp,dist_temp,fare2_temp,min_temp,sec_temp:STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL  speed1,min1,sec1,unipri1,strpri1:STD_LOGIC_VECTOR(7 downto 0);
	
BEGIN
cin_temp<='0';
speed1<="000000"&speed;
sec1<="00"&sec;
min1<="00"&min;
unipri1<="000000"&unipri;
strpri1<="0000"&strpri;
flag10_temp<=not start_temp;
U1:count60 PORT MAP(clk,clr,start, sec, temp);
U2:count60 PORT MAP(temp,clr,start,min,hor_temp);
U3:multi8  PORT MAP(quiclk,temp,speed1,min1,start_temp,dist);
U4:multi8  PORT MAP(quiclk,flag10_temp,unipri1,dist(7  DOWNTO 0),multi_temp,fare1);
U5:add8    PORT MAP(cin_temp,fare1(7  DOWNTO 0),strpri1, fare2,cout_temp);
U6:decoder3_8 PORT MAP(quiclk,wei8_temp);
U7:changebcd PORT MAP(sec1(6  DOWNTO 0),sec_temp);
U8:changebcd PORT MAP(min1(6  DOWNTO 0),min_temp);
U9:changebcd PORT MAP(strpri1(6 DOWNTO 0),strpri_temp);
U10:changebcd PORT MAP(dist(6  DOWNTO  0),dist_temp);
U11:changebcd PORT MAP(fare2(6  DOWNTO  0),fare2_temp);
U12:duanxuan  PORT MAP(wei8_temp, strpri_temp,fare2_temp,sec_temp,min_temp,
                       unipri,start,seg);
wei8<=wei8_temp;
dist1<=dist_temp;
END  execute;