📄 hedfile.rpt
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D16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
D19 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
D20 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
D21 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
D22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D23 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
D24 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
E2 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
E3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E5 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
E6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E8 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
E9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
E10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E11 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
E12 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
E14 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
E16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
E17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
E19 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
E20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E21 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
E23 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
E24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
F4 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
F5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
F7 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 13/22( 59%)
F8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F11 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
F12 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
F13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F17 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 13/22( 59%)
F18 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
F19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F22 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
F23 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F24 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 29/96 ( 30%)
Total logic cells used: 397/1152 ( 34%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 1341/4608 ( 29%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 23
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 397
Total flipflops required: 70
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 109/1152 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 7 7 7 7 4 1 1 1 1 0 4 0 0 1 3 5 1 8 4 1 1 1 1 1 67/0
B: 0 1 1 1 7 1 1 0 6 3 6 1 0 0 0 1 7 0 8 3 8 6 1 6 1 69/0
C: 5 2 1 1 1 3 7 1 1 2 4 1 0 8 1 1 1 2 1 5 8 6 1 1 4 68/0
D: 0 1 8 1 1 1 1 5 3 4 1 1 0 1 1 1 1 1 1 6 6 6 1 7 7 66/0
E: 0 7 1 1 5 1 1 4 1 1 6 6 0 0 6 0 1 1 0 3 1 6 0 5 1 58/0
F: 0 1 0 7 1 0 7 1 1 1 3 6 0 1 0 1 1 6 3 1 8 1 7 5 7 69/0
Total: 5 19 18 18 22 10 18 12 13 12 20 19 0 10 9 7 16 11 21 22 32 26 11 25 21 397/0
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\hedfile.rpt
hedfile
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G 0 0 0 0 clk
56 - - - -- INPUT G 0 0 0 0 clr
55 - - - -- INPUT G 0 0 0 4 quiclk
144 - - A -- INPUT 0 0 0 2 speed0
143 - - A -- INPUT 0 0 0 2 speed1
126 - - - -- INPUT 0 0 0 25 start
110 - - - 01 INPUT 0 0 0 4 strpri0
54 - - - -- INPUT 0 0 0 6 strpri1
111 - - - 01 INPUT 0 0 0 6 strpri2
124 - - - -- INPUT 0 0 0 7 strpri3
73 - - - 01 INPUT 0 0 0 3 unipri0
112 - - - 02 INPUT 0 0 0 3 unipri1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\hedfile.rpt
hedfile
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - E -- OUTPUT 0 1 0 0 dist10
82 - - E -- OUTPUT 0 1 0 0 dist11
86 - - E -- OUTPUT 0 1 0 0 dist12
87 - - E -- OUTPUT 0 1 0 0 dist13
83 - - E -- OUTPUT 0 1 0 0 dist14
26 - - E -- OUTPUT 0 1 0 0 dist15
27 - - E -- OUTPUT 0 1 0 0 dist16
29 - - E -- OUTPUT 0 1 0 0 dist17
14 - - C -- OUTPUT 0 1 0 0 seg0
90 - - C -- OUTPUT 0 1 0 0 seg1
122 - - - 13 OUTPUT 0 1 0 0 seg2
128 - - - 13 OUTPUT 0 1 0 0 seg3
46 - - - 17 OUTPUT 0 1 0 0 seg4
39 - - - 21 OUTPUT 0 1 0 0 seg5
133 - - - 18 OUTPUT 0 1 0 0 seg6
101 - - A -- OUTPUT 0 1 0 0 wei80
12 - - C -- OUTPUT 0 1 0 0 wei81
67 - - - 08 OUTPUT 0 1 0 0 wei82
11 - - C -- OUTPUT 0 1 0 0 wei83
13 - - C -- OUTPUT 0 1 0 0 wei84
91 - - C -- OUTPUT 0 1 0 0 wei85
89 - - C -- OUTPUT 0 1 0 0 wei86
92 - - C -- OUTPUT 0 1 0 0 wei87
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\hedfile.rpt
hedfile
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 04 OR2 2 2 0 2 |add8:U5|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry1
- 3 - A 04 OR2 1 2 0 3 |add8:U5|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry2
- 1 - A 04 OR2 2 2 0 4 |add8:U5|add4:U1|LPM_ADD_SUB:50|addcore:adder|:88
- 2 - A 04 OR2 1 2 0 14 |add8:U5|add4:U1|LPM_ADD_SUB:50|addcore:adder|:89
- 1 - A 09 OR2 1 2 0 22 |add8:U5|add4:U1|LPM_ADD_SUB:50|addcore:adder|:90
- 2 - A 06 OR2 1 3 0 4 |add8:U5|add4:U2|LPM_ADD_SUB:51|addcore:adder|:52
- 1 - A 06 OR2 1 3 0 14 |add8:U5|add4:U2|LPM_ADD_SUB:51|addcore:adder|:73
- 2 - B 04 OR2 0 2 0 9 |add8:U5|add4:U2|LPM_ADD_SUB:51|addcore:adder|:75
- 6 - B 09 OR2 s ! 0 3 0 1 |add8:U5|add4:U2|LPM_ADD_SUB:51|addcore:adder|~76~1
- 1 - B 02 OR2 0 3 0 7 |add8:U5|add4:U2|LPM_ADD_SUB:51|addcore:adder|:76
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