📄 hedfile.rpt
字号:
|changebcd:U11|lpm_add_sub:1481|altshift:carry_ext_latency_ffs|
|changebcd:U11|lpm_add_sub:1481|altshift:oflow_ext_latency_ffs|
|duanxuan:U12|
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\hedfile.rpt
hedfile
***** Logic for device 'hedfile' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E s E E E E E E E E u s s E
s s S S S S S S S S S S G t V S S S S S S S S n t t S
p p E E E G E E E E V E E E G N s r C E E E E E E V E E i r r E
e e R R R N R R R R C s R R R N s D t p C s R R R R R R C R R p p p R
e e V V V D V V V V C e V V V D e I a c r I e V V V V V V C V V r r r V
d d E E E I E E E E I g E E E I g N r l i N g E E E E E E I E E i i i E
0 1 D D D O D D D D O 6 D D D O 3 T t k 3 T 2 D D D D D D O D D 1 2 0 D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | wei80
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
wei83 | 11 98 | RESERVED
wei81 | 12 97 | RESERVED
wei84 | 13 96 | RESERVED
seg0 | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | wei87
RESERVED | 18 91 | wei85
RESERVED | 19 EPF10K20TC144-3 90 | seg1
RESERVED | 20 89 | wei86
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | dist13
RESERVED | 23 86 | dist12
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
dist15 | 26 83 | dist14
dist16 | 27 82 | dist11
dist10 | 28 81 | RESERVED
dist17 | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | unipri0
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R s G R R R R V s R R R G R V V s q c G G R R V R R R R G w R R R V R
E E e N E E E E C e E E E N E C C t u l N N E E C E E E E N e E E E C E
S S g D S S S S C g S S S D S C C r i r D D S S C S S S S D i S S S C S
E E 5 I E E E E I 4 E E E I E I I p c I I E E I E E E E I 8 E E E I E
R R O R R R R O R R R O R N N r l N N R R O R R R R O 2 R R R O R
V V V V V V V V V V T T i k T T V V V V V V V V V V
E E E E E E E E E E 1 E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\hedfile.rpt
hedfile
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A3 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
A4 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
A5 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A6 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A12 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A15 3/ 8( 37%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 3/22( 13%)
A16 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
A19 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A21 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A22 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A23 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A24 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B5 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
B6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B9 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B10 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
B11 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B16 7/ 8( 87%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 11/22( 50%)
B18 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
B19 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
B20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
B21 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
B22 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B23 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C1 5/ 8( 62%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C2 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C5 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C6 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
C7 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
C8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C10 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C11 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C17 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C19 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 14/22( 63%)
C20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
C21 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C24 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
D3 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
D4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
D8 5/ 8( 62%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 6/22( 27%)
D9 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
D10 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
D11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
D12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
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