📄 add8.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY add8 IS
PORT(
cin:IN STD_LOGIC;
a,b :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cout:OUT STD_LOGIC);
END add8;
ARCHITECTURE struc OF add8 IS
COMPONENT add4
PORT(
cin:IN STD_LOGIC;
a,b :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout:OUT STD_LOGIC);
END COMPONENT;
SIGNAL carry_out:STD_LOGIC;
BEGIN
U1:add4 PORT MAP(cin,a(3 DOWNTO 0),b(3 DOWNTO 0),s(3 DOWNTO 0),carry_out);
U2:add4 PORT MAP(carry_out,a(7 DOWNTO 4),b(7 DOWNTO 4),s(7 DOWNTO 4),cout);
END struc;
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