📄 add8.rpt
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# !a0 & b0 & !cin
# a0 & b0 & cin
# !a0 & !b0 & cin;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ007);
_EQ007 = a0 & !b0 & cin & !_LC1_A3
# !a0 & b0 & cin & !_LC1_A3
# a0 & b0 & _LC1_A3
# !a0 & !b0 & _LC1_A3
# !cin & _LC1_A3;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ008);
_EQ008 = a2 & !b2 & !_LC4_A1 & !_LC6_A1
# !a2 & b2 & !_LC4_A1 & !_LC6_A1
# a2 & b2 & _LC4_A1 & !_LC6_A1
# !a2 & !b2 & _LC4_A1 & !_LC6_A1
# a2 & !b2 & _LC4_A1 & _LC6_A1
# !a2 & b2 & _LC4_A1 & _LC6_A1
# a2 & b2 & !_LC4_A1 & _LC6_A1
# !a2 & !b2 & !_LC4_A1 & _LC6_A1;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ009);
_EQ009 = !a3 & b3 & !_LC5_A1 & !_LC7_A1
# a3 & !b3 & !_LC5_A1 & !_LC7_A1
# a3 & b3 & !_LC5_A1 & _LC7_A1
# !a3 & !b3 & !_LC5_A1 & _LC7_A1
# !a3 & b3 & _LC5_A1 & _LC7_A1
# a3 & !b3 & _LC5_A1 & _LC7_A1
# a3 & b3 & _LC5_A1 & !_LC7_A1
# !a3 & !b3 & _LC5_A1 & !_LC7_A1;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ010);
_EQ010 = !a3 & _LC5_A1 & _LC7_A1
# a3 & !b3 & _LC5_A1
# !a3 & b3 & _LC5_A1
# !a3 & b3 & _LC7_A1
# a3 & !b3 & _LC7_A1
# a3 & b3 & !_LC7_A1
# b3 & !_LC5_A1 & _LC7_A1
# a3 & !_LC5_A1 & _LC7_A1
# a3 & b3 & !_LC5_A1;
-- Node name is '|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ011);
_EQ011 = a5 & b5
# a4 & b4 & b5
# a4 & a5 & b4;
-- Node name is '|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ012);
_EQ012 = a6 & _LC7_A13
# b6 & _LC7_A13
# a6 & b6;
-- Node name is '|add4:U2|LPM_ADD_SUB:50|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ013);
_EQ013 = a4 & !a5 & b4 & !b5
# !a4 & !a5 & b5
# !a5 & !b4 & b5
# a4 & a5 & b4 & b5
# !a4 & a5 & !b5
# a5 & !b4 & !b5;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ014);
_EQ014 = a4 & !b4 & _LC1_A15 & _LC2_A1
# !a4 & b4 & _LC1_A15 & _LC2_A1;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ015);
_EQ015 = a6 & !b6 & _LC5_A13 & !_LC7_A13
# !a6 & b6 & _LC5_A13 & !_LC7_A13
# a6 & b6 & _LC5_A13 & _LC7_A13
# !a6 & !b6 & _LC5_A13 & _LC7_A13;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ016);
_EQ016 = a4 & !b4 & !_LC2_A1
# !a4 & b4 & !_LC2_A1
# a4 & b4 & _LC2_A1
# !a4 & !b4 & _LC2_A1;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ017);
_EQ017 = a4 & !b4 & !_LC1_A15 & _LC2_A1
# !a4 & b4 & !_LC1_A15 & _LC2_A1
# a4 & b4 & _LC1_A15
# !a4 & !b4 & _LC1_A15
# _LC1_A15 & !_LC2_A1;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ018);
_EQ018 = a6 & !b6 & !_LC5_A13 & !_LC7_A13
# !a6 & b6 & !_LC5_A13 & !_LC7_A13
# a6 & b6 & !_LC5_A13 & _LC7_A13
# !a6 & !b6 & !_LC5_A13 & _LC7_A13
# a6 & !b6 & _LC5_A13 & _LC7_A13
# !a6 & b6 & _LC5_A13 & _LC7_A13
# a6 & b6 & _LC5_A13 & !_LC7_A13
# !a6 & !b6 & _LC5_A13 & !_LC7_A13;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ019);
_EQ019 = !a7 & b7 & !_LC2_A13 & !_LC6_A13
# a7 & !b7 & !_LC2_A13 & !_LC6_A13
# a7 & b7 & !_LC2_A13 & _LC6_A13
# !a7 & !b7 & !_LC2_A13 & _LC6_A13
# !a7 & b7 & _LC2_A13 & _LC6_A13
# a7 & !b7 & _LC2_A13 & _LC6_A13
# a7 & b7 & _LC2_A13 & !_LC6_A13
# !a7 & !b7 & _LC2_A13 & !_LC6_A13;
-- Node name is '|add4:U2|LPM_ADD_SUB:51|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ020);
_EQ020 = !a7 & _LC2_A13 & _LC6_A13
# a7 & !b7 & _LC2_A13
# !a7 & b7 & _LC2_A13
# !a7 & b7 & _LC6_A13
# a7 & !b7 & _LC6_A13
# a7 & b7 & !_LC6_A13
# b7 & !_LC2_A13 & _LC6_A13
# a7 & !_LC2_A13 & _LC6_A13
# a7 & b7 & !_LC2_A13;
Project Information f:\zztt\vhdl\designtaxi_25\add8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,837K
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