📄 add8.rpt
字号:
70 - - A -- INPUT 0 0 0 3 b2
17 - - A -- INPUT 0 0 0 2 b3
42 - - - -- INPUT 0 0 0 5 b4
71 - - A -- INPUT 0 0 0 2 b5
19 - - A -- INPUT 0 0 0 3 b6
48 - - - 15 INPUT 0 0 0 2 b7
73 - - A -- INPUT 0 0 0 3 cin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\add8.rpt
add8
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
61 - - C -- OUTPUT 0 1 0 0 cout
9 - - - 02 OUTPUT 0 1 0 0 s0
11 - - - 01 OUTPUT 0 1 0 0 s1
10 - - - 01 OUTPUT 0 1 0 0 s2
28 - - C -- OUTPUT 0 1 0 0 s3
66 - - B -- OUTPUT 0 1 0 0 s4
47 - - - 14 OUTPUT 0 1 0 0 s5
83 - - - 13 OUTPUT 0 1 0 0 s6
60 - - C -- OUTPUT 0 1 0 0 s7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\add8.rpt
add8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 01 OR2 4 0 0 3 |add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry1
- 7 - A 01 OR2 2 1 0 2 |add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry2
- 1 - A 03 OR2 4 0 0 2 |add4:U1|LPM_ADD_SUB:50|addcore:adder|:88
- 6 - A 01 OR2 3 1 0 2 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:59
- 5 - A 01 OR2 2 2 0 2 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:63
- 1 - A 02 OR2 3 0 1 0 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:73
- 2 - A 02 OR2 3 1 1 0 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:75
- 1 - A 01 OR2 2 2 1 0 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:76
- 3 - A 01 OR2 2 2 1 0 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:77
- 2 - A 01 OR2 2 2 0 3 |add4:U1|LPM_ADD_SUB:51|addcore:adder|:78
- 7 - A 13 OR2 4 0 0 3 |add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry1
- 6 - A 13 OR2 2 1 0 2 |add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry2
- 1 - A 15 OR2 4 0 0 2 |add4:U2|LPM_ADD_SUB:50|addcore:adder|:88
- 5 - A 13 OR2 2 2 0 2 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:59
- 2 - A 13 OR2 2 2 0 2 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:63
- 2 - A 14 OR2 2 1 1 0 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:73
- 1 - A 14 OR2 2 2 1 0 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:75
- 1 - A 13 OR2 2 2 1 0 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:76
- 4 - A 13 OR2 2 2 1 0 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:77
- 3 - A 13 OR2 2 2 1 0 |add4:U2|LPM_ADD_SUB:51|addcore:adder|:78
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\add8.rpt
add8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 2/ 48( 4%) 2/ 48( 4%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\add8.rpt
add8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
cin : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC3_A13;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC1_A2;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC2_A2;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC1_A1;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC3_A1;
-- Node name is 's4'
-- Equation name is 's4', type is output
s4 = _LC2_A14;
-- Node name is 's5'
-- Equation name is 's5', type is output
s5 = _LC1_A14;
-- Node name is 's6'
-- Equation name is 's6', type is output
s6 = _LC1_A13;
-- Node name is 's7'
-- Equation name is 's7', type is output
s7 = _LC4_A13;
-- Node name is '|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ001);
_EQ001 = a1 & b1
# a0 & b0 & b1
# a0 & a1 & b0;
-- Node name is '|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ002);
_EQ002 = a2 & _LC4_A1
# b2 & _LC4_A1
# a2 & b2;
-- Node name is '|add4:U1|LPM_ADD_SUB:50|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ003);
_EQ003 = a0 & !a1 & b0 & !b1
# !a0 & !a1 & b1
# !a1 & !b0 & b1
# a0 & a1 & b0 & b1
# !a0 & a1 & !b1
# a1 & !b0 & !b1;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ004);
_EQ004 = a0 & !b0 & cin & _LC1_A3
# !a0 & b0 & cin & _LC1_A3;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ005);
_EQ005 = a2 & !b2 & !_LC4_A1 & _LC6_A1
# !a2 & b2 & !_LC4_A1 & _LC6_A1
# a2 & b2 & _LC4_A1 & _LC6_A1
# !a2 & !b2 & _LC4_A1 & _LC6_A1;
-- Node name is '|add4:U1|LPM_ADD_SUB:51|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ006);
_EQ006 = a0 & !b0 & !cin
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