changebcd.rpt

出租车计费器,VHDL实现

-- Node name is '~1587~2' 
-- Equation name is '~1587~2', location is LC2_A6, type is buried.
-- synthesized logic cell 
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ026);
  _EQ026 =  _LC1_A2
         #  _LC1_A6;

-- Node name is ':1587' 
-- Equation name is '_LC6_A10', type is buried 
_LC6_A10 = LCELL( _EQ027);
  _EQ027 =  _LC1_C12 & !_LC2_B2
         # !_LC2_B2 &  _LC3_C1;

-- Node name is '~1606~1' 
-- Equation name is '~1606~1', location is LC1_C7, type is buried.
-- synthesized logic cell 
_LC1_C7  = LCELL( _EQ028);
  _EQ028 =  _LC2_C4
         #  _LC1_C4;

-- Node name is ':1620' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ029);
  _EQ029 =  _LC1_A12 &  _LC1_C7 &  _LC2_A6
         #  _LC1_A12 &  _LC1_B2 &  _LC2_A6;

-- Node name is ':1633' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ030);
  _EQ030 =  _LC1_C1
         #  _LC2_C1;

-- Node name is ':1653' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ031);
  _EQ031 =  _LC1_B2 & !_LC1_C7 &  _LC2_A6
         # !_LC1_A12 &  _LC2_A6;

-- Node name is ':1686' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ032);
  _EQ032 = !_LC1_A2 &  _LC2_A3 & !_LC2_A5
         # !_LC1_A2 &  _LC1_A6;

-- Node name is ':1792' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ033);
  _EQ033 =  dat3 &  _LC1_A9 &  _LC3_C1
         # !dat3 & !_LC1_A9 & !_LC1_C12 &  _LC3_C1
         #  dat3 &  _LC1_C12;

-- Node name is ':1795' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ034);
  _EQ034 =  dat3 & !_LC1_A8 &  _LC1_C1
         # !dat3 &  _LC1_A8 &  _LC1_C1
         # !_LC1_C1 &  _LC7_C5;

-- Node name is ':1798' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = LCELL( _EQ035);
  _EQ035 = !_LC2_C1 &  _LC5_C5
         # !dat2 &  dat3 &  _LC2_C1
         #  dat2 & !dat3 &  _LC2_C1;

-- Node name is ':1801' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ036);
  _EQ036 = !_LC2_C4 &  _LC4_C5
         #  dat3 & !_LC1_A9 &  _LC2_C4
         # !dat3 &  _LC1_A9 &  _LC2_C4;

-- Node name is ':1804' 
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ037);
  _EQ037 = !_LC1_C4 &  _LC2_C5
         # !dat3 &  _LC1_C4;

-- Node name is ':1807' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = LCELL( _EQ038);
  _EQ038 = !_LC1_A5 &  _LC6_C5
         # !dat3 &  _LC1_A5 & !_LC1_A8
         #  dat3 &  _LC1_A5 &  _LC1_A8;

-- Node name is ':1810' 
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = LCELL( _EQ039);
  _EQ039 = !_LC2_A5 &  _LC3_A5
         #  dat2 &  dat3 &  _LC2_A5
         # !dat2 & !dat3 &  _LC2_A5;

-- Node name is ':1813' 
-- Equation name is '_LC4_A5', type is buried 
_LC4_A5  = LCELL( _EQ040);
  _EQ040 = !_LC1_A6 &  _LC5_A5
         #  dat3 &  _LC1_A6 &  _LC1_A9
         # !dat3 &  _LC1_A6 & !_LC1_A9;

-- Node name is ':1816' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ041);
  _EQ041 = !_LC1_A2 &  _LC4_A5
         #  dat3 &  _LC1_A2;

-- Node name is ':1825' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ042);
  _EQ042 =  dat1 &  dat2 &  _LC3_C1
         # !dat1 & !dat2 & !_LC1_C12 &  _LC3_C1
         #  dat2 &  _LC1_C12;

-- Node name is ':1828' 
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ043);
  _EQ043 = !_LC1_C1 &  _LC2_A4
         # !dat1 &  dat2 &  _LC1_C1
         #  dat1 & !dat2 &  _LC1_C1;

-- Node name is ':1831' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = LCELL( _EQ044);
  _EQ044 = !_LC2_C1 &  _LC4_A4
         # !dat2 &  _LC2_C1;

-- Node name is ':1834' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ045);
  _EQ045 = !_LC2_C4 &  _LC3_A4
         #  dat1 &  dat2 &  _LC2_C4
         # !dat1 & !dat2 &  _LC2_C4;

-- Node name is ':1837' 
-- Equation name is '_LC3_A7', type is buried 
_LC3_A7  = LCELL( _EQ046);
  _EQ046 =  _LC1_A4 & !_LC1_C4
         #  dat2 &  _LC1_C4;

-- Node name is ':1840' 
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = LCELL( _EQ047);
  _EQ047 = !_LC1_A5 &  _LC3_A7
         # !dat1 &  dat2 &  _LC1_A5
         #  dat1 & !dat2 &  _LC1_A5;

-- Node name is ':1843' 
-- Equation name is '_LC1_A7', type is buried 
_LC1_A7  = LCELL( _EQ048);
  _EQ048 = !_LC2_A5 &  _LC2_A7
         # !dat2 &  _LC2_A5;

-- Node name is ':1846' 
-- Equation name is '_LC4_A7', type is buried 
_LC4_A7  = LCELL( _EQ049);
  _EQ049 = !_LC1_A6 &  _LC1_A7
         #  dat1 &  dat2 &  _LC1_A6
         # !dat1 & !dat2 &  _LC1_A6;

-- Node name is ':1849' 
-- Equation name is '_LC5_A7', type is buried 
_LC5_A7  = LCELL( _EQ050);
  _EQ050 = !_LC1_A2 &  _LC4_A7
         #  dat2 &  _LC1_A2;

-- Node name is '~1882~1' 
-- Equation name is '~1882~1', location is LC4_A3, type is buried.
-- synthesized logic cell 
_LC4_A3  = LCELL( _EQ051);
  _EQ051 = !_LC1_C12 & !_LC2_C1 &  _LC3_C1
         #  _LC1_C1 & !_LC2_C1;

-- Node name is '~1882~2' 
-- Equation name is '~1882~2', location is LC2_A3, type is buried.
-- synthesized logic cell 
_LC2_A3  = LCELL( _EQ052);
  _EQ052 = !_LC1_C4 &  _LC4_A3
         # !_LC1_C4 &  _LC2_C4
         #  _LC1_A5;

-- Node name is '~1882~3' 
-- Equation name is '~1882~3', location is LC1_C5, type is buried.
-- synthesized logic cell 
_LC1_C5  = LCELL( _EQ053);
  _EQ053 = !_LC1_C1 &  _LC1_C12
         #  _LC2_C1;

-- Node name is '~1882~4' 
-- Equation name is '~1882~4', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ054);
  _EQ054 =  _LC1_C5 & !_LC2_C4
         #  _LC1_C4;

-- Node name is '~1882~5' 
-- Equation name is '~1882~5', location is LC1_A3, type is buried.
-- synthesized logic cell 
_LC1_A3  = LCELL( _EQ055);
  _EQ055 = !_LC1_A5 & !_LC1_A6 &  _LC3_C5
         # !_LC1_A6 &  _LC2_A5;

-- Node name is ':1882' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = LCELL( _EQ056);
  _EQ056 = !dat1 &  _LC5_A3
         #  dat1 &  _LC1_A3
         #  dat1 &  _LC1_A2;

-- Node name is '~1915~1' 
-- Equation name is '~1915~1', location is LC2_B2, type is buried.
-- synthesized logic cell 
_LC2_B2  = LCELL( _EQ057);
  _EQ057 =  _LC1_C7
         #  _LC1_B2
         # !_LC1_A12
         # !_LC2_A6;

-- Node name is ':1915' 
-- Equation name is '_LC8_A11', type is buried 
_LC8_A11 = LCELL( _EQ058);
  _EQ058 =  dat0 &  _LC2_B2
         #  dat0 &  _LC1_C12
         #  dat0 &  _LC3_C1;



Project Information                   f:\zztt\vhdl\designtaxi_25\changebcd.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,963K