📄 changebcd.rpt
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IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 02 AND2 3 1 0 5 :318
- 3 - A 06 OR2 s ! 3 1 0 1 ~427~1
- 1 - A 06 AND2 2 1 0 5 :427
- 6 - A 05 OR2 s ! 3 1 0 1 ~507~1
- 2 - A 05 AND2 2 1 0 5 :507
- 6 - C 08 AND2 2 0 0 3 :562
- 7 - A 05 OR2 s ! 3 1 0 1 ~587~1
- 1 - A 05 AND2 1 1 0 5 :587
- 3 - C 04 OR2 2 1 0 2 :645
- 1 - C 04 AND2 2 2 0 5 :667
- 4 - C 04 OR2 2 0 0 1 :730
- 2 - C 04 AND2 2 2 0 5 :747
- 8 - C 01 AND2 ! 4 0 0 1 :760
- 7 - C 01 AND2 1 2 0 1 :797
- 1 - A 08 OR2 2 0 0 6 :815
- 2 - C 01 OR2 1 2 0 5 :827
- 1 - C 01 OR2 2 2 0 5 :907
- 2 - C 06 AND2 ! 1 1 0 4 :970
- 6 - C 01 AND2 s 2 0 0 1 ~987~1
- 1 - C 12 AND2 3 1 0 6 :987
- 1 - A 09 OR2 ! 2 0 0 5 :1012
- 5 - C 01 AND2 s 2 1 0 1 ~1067~1
- 4 - C 01 AND2 s 2 1 0 1 ~1067~2
- 3 - C 01 OR2 1 2 0 5 :1067
- 1 - A 12 OR2 s ! 0 2 0 3 ~1587~1
- 2 - A 06 OR2 s ! 0 2 0 3 ~1587~2
- 6 - A 10 OR2 0 3 1 0 :1587
- 1 - C 07 OR2 s 0 2 0 3 ~1606~1
- 5 - B 02 OR2 0 4 1 0 :1620
- 1 - B 02 OR2 0 2 0 3 :1633
- 3 - B 02 OR2 0 4 1 0 :1653
- 5 - A 03 OR2 0 4 1 1 :1686
- 7 - C 05 OR2 1 3 0 1 :1792
- 5 - C 05 OR2 1 3 0 1 :1795
- 4 - C 05 OR2 2 2 0 1 :1798
- 2 - C 05 OR2 1 3 0 1 :1801
- 6 - C 05 OR2 1 2 0 1 :1804
- 3 - A 05 OR2 1 3 0 1 :1807
- 5 - A 05 OR2 2 2 0 1 :1810
- 4 - A 05 OR2 1 3 0 1 :1813
- 4 - A 13 OR2 1 2 1 0 :1816
- 2 - A 04 OR2 2 2 0 1 :1825
- 4 - A 04 OR2 2 2 0 1 :1828
- 3 - A 04 OR2 1 2 0 1 :1831
- 1 - A 04 OR2 2 2 0 1 :1834
- 3 - A 07 OR2 1 2 0 1 :1837
- 2 - A 07 OR2 2 2 0 1 :1840
- 1 - A 07 OR2 1 2 0 1 :1843
- 4 - A 07 OR2 2 2 0 1 :1846
- 5 - A 07 OR2 1 2 1 0 :1849
- 4 - A 03 OR2 s 0 4 0 1 ~1882~1
- 2 - A 03 OR2 s 0 4 0 1 ~1882~2
- 1 - C 05 OR2 s 0 3 0 1 ~1882~3
- 3 - C 05 OR2 s 0 3 0 1 ~1882~4
- 1 - A 03 OR2 s 0 4 0 1 ~1882~5
- 3 - A 03 OR2 1 3 1 0 :1882
- 2 - B 02 OR2 s 0 4 0 2 ~1915~1
- 8 - A 11 OR2 1 3 1 0 :1915
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\changebcd.rpt
changebcd
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 19/ 48( 39%) 1/ 48( 2%) 1/16( 6%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\changebcd.rpt
changebcd
** EQUATIONS **
dat0 : INPUT;
dat1 : INPUT;
dat2 : INPUT;
dat3 : INPUT;
dat4 : INPUT;
dat5 : INPUT;
dat6 : INPUT;
-- Node name is 'bcd0'
-- Equation name is 'bcd0', type is output
bcd0 = _LC8_A11;
-- Node name is 'bcd1'
-- Equation name is 'bcd1', type is output
bcd1 = _LC3_A3;
-- Node name is 'bcd2'
-- Equation name is 'bcd2', type is output
bcd2 = _LC5_A7;
-- Node name is 'bcd3'
-- Equation name is 'bcd3', type is output
bcd3 = _LC4_A13;
-- Node name is 'bcd4'
-- Equation name is 'bcd4', type is output
bcd4 = _LC5_A3;
-- Node name is 'bcd5'
-- Equation name is 'bcd5', type is output
bcd5 = _LC3_B2;
-- Node name is 'bcd6'
-- Equation name is 'bcd6', type is output
bcd6 = _LC5_B2;
-- Node name is 'bcd7'
-- Equation name is 'bcd7', type is output
bcd7 = _LC6_A10;
-- Node name is ':318'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ001);
_EQ001 = !dat4 & !dat5 & !dat6 & _LC2_C6;
-- Node name is '~427~1'
-- Equation name is '~427~1', location is LC3_A6, type is buried.
-- synthesized logic cell
!_LC3_A6 = _LC3_A6~NOT;
_LC3_A6~NOT = LCELL( _EQ002);
_EQ002 = !dat2 & !dat3 & !_LC2_C6
# !dat4 & !_LC2_C6
# !dat2 & !dat3 & dat4;
-- Node name is ':427'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ003);
_EQ003 = !dat5 & !dat6 & !_LC3_A6;
-- Node name is '~507~1'
-- Equation name is '~507~1', location is LC6_A5, type is buried.
-- synthesized logic cell
!_LC6_A5 = _LC6_A5~NOT;
_LC6_A5~NOT = LCELL( _EQ004);
_EQ004 = dat3 & dat4 & _LC1_A8
# dat2 & dat4 & _LC1_A8
# dat2 & !dat3 & dat4;
-- Node name is ':507'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ005);
_EQ005 = !dat5 & !dat6 & !_LC6_A5;
-- Node name is ':562'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ006);
_EQ006 = !dat3 & !dat4;
-- Node name is '~587~1'
-- Equation name is '~587~1', location is LC7_A5, type is buried.
-- synthesized logic cell
!_LC7_A5 = _LC7_A5~NOT;
_LC7_A5~NOT = LCELL( _EQ007);
_EQ007 = dat3 & dat4 & !dat5 & !_LC1_A8
# !dat3 & !dat4 & dat5;
-- Node name is ':587'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ008);
_EQ008 = !dat6 & !_LC7_A5;
-- Node name is ':645'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ009);
_EQ009 = !dat3 & _LC1_A9
# !dat4;
-- Node name is ':667'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ010);
_EQ010 = dat5 & !dat6 & _LC3_C4 & !_LC6_C8;
-- Node name is ':730'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = LCELL( _EQ011);
_EQ011 = !dat3
# !dat2;
-- Node name is ':747'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ012);
_EQ012 = dat5 & !dat6 & !_LC3_C4 & _LC4_C4;
-- Node name is ':760'
-- Equation name is '_LC8_C1', type is buried
!_LC8_C1 = _LC8_C1~NOT;
_LC8_C1~NOT = LCELL( _EQ013);
_EQ013 = dat2 & dat3 & dat4 & dat5;
-- Node name is ':797'
-- Equation name is '_LC7_C1', type is buried
_LC7_C1 = LCELL( _EQ014);
_EQ014 = !dat5 & _LC1_A8 & _LC6_C8;
-- Node name is ':815'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = LCELL( _EQ015);
_EQ015 = !dat2
# !dat1;
-- Node name is ':827'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ016);
_EQ016 = _LC7_C1 & !_LC8_C1
# !dat6 & !_LC8_C1
# dat6 & _LC7_C1;
-- Node name is ':907'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ017);
_EQ017 = !dat4 & !_LC1_A8 & _LC6_C1
# dat3 & !dat4 & _LC6_C1;
-- Node name is ':970'
-- Equation name is '_LC2_C6', type is buried
!_LC2_C6 = _LC2_C6~NOT;
_LC2_C6~NOT = LCELL( _EQ018);
_EQ018 = dat3 & !_LC1_A9;
-- Node name is '~987~1'
-- Equation name is '~987~1', location is LC6_C1, type is buried.
-- synthesized logic cell
_LC6_C1 = LCELL( _EQ019);
_EQ019 = !dat5 & dat6;
-- Node name is ':987'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ020);
_EQ020 = dat4 & !dat5 & dat6 & _LC2_C6;
-- Node name is ':1012'
-- Equation name is '_LC1_A9', type is buried
!_LC1_A9 = _LC1_A9~NOT;
_LC1_A9~NOT = LCELL( _EQ021);
_EQ021 = dat2
# dat1;
-- Node name is '~1067~1'
-- Equation name is '~1067~1', location is LC5_C1, type is buried.
-- synthesized logic cell
_LC5_C1 = LCELL( _EQ022);
_EQ022 = !dat2 & dat5 & _LC6_C8;
-- Node name is '~1067~2'
-- Equation name is '~1067~2', location is LC4_C1, type is buried.
-- synthesized logic cell
_LC4_C1 = LCELL( _EQ023);
_EQ023 = dat4 & !dat5 & !_LC2_C6;
-- Node name is ':1067'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ024);
_EQ024 = dat6 & _LC5_C1
# dat6 & _LC4_C1;
-- Node name is '~1587~1'
-- Equation name is '~1587~1', location is LC1_A12, type is buried.
-- synthesized logic cell
!_LC1_A12 = _LC1_A12~NOT;
_LC1_A12~NOT = LCELL( _EQ025);
_EQ025 = _LC1_A5
# _LC2_A5;
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