📄 reg16.rpt
字号:
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 4/ 48( 8%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 8/24( 33%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\reg16.rpt
reg16
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\reg16.rpt
reg16
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 clr
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\reg16.rpt
reg16
** EQUATIONS **
clk : INPUT;
clr : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = r16s0;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = r16s1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = r16s2;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = r16s3;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = r16s4;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = r16s5;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = r16s6;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = r16s7;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = r16s8;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = r16s9;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = r16s10;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = r16s11;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = r16s12;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = r16s13;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = r16s14;
-- Node name is 'q15'
-- Equation name is 'q15', type is output
q15 = r16s15;
-- Node name is ':43' = 'r16s0'
-- Equation name is 'r16s0', location is LC8_A1, type is buried.
r16s0 = DFFE( r16s1, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':42' = 'r16s1'
-- Equation name is 'r16s1', location is LC7_A1, type is buried.
r16s1 = DFFE( r16s2, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':41' = 'r16s2'
-- Equation name is 'r16s2', location is LC6_A1, type is buried.
r16s2 = DFFE( r16s3, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':40' = 'r16s3'
-- Equation name is 'r16s3', location is LC5_A1, type is buried.
r16s3 = DFFE( r16s4, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':39' = 'r16s4'
-- Equation name is 'r16s4', location is LC4_A1, type is buried.
r16s4 = DFFE( r16s5, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':38' = 'r16s5'
-- Equation name is 'r16s5', location is LC3_A1, type is buried.
r16s5 = DFFE( r16s6, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':37' = 'r16s6'
-- Equation name is 'r16s6', location is LC2_A1, type is buried.
r16s6 = DFFE( r16s7, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':36' = 'r16s7'
-- Equation name is 'r16s7', location is LC1_A1, type is buried.
r16s7 = DFFE( d0, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':35' = 'r16s8'
-- Equation name is 'r16s8', location is LC1_A4, type is buried.
r16s8 = DFFE( d1, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':34' = 'r16s9'
-- Equation name is 'r16s9', location is LC5_A5, type is buried.
r16s9 = DFFE( d2, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':33' = 'r16s10'
-- Equation name is 'r16s10', location is LC6_A6, type is buried.
r16s10 = DFFE( d3, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':32' = 'r16s11'
-- Equation name is 'r16s11', location is LC3_A7, type is buried.
r16s11 = DFFE( d4, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':31' = 'r16s12'
-- Equation name is 'r16s12', location is LC1_A2, type is buried.
r16s12 = DFFE( d5, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':30' = 'r16s13'
-- Equation name is 'r16s13', location is LC2_A2, type is buried.
r16s13 = DFFE( d6, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':29' = 'r16s14'
-- Equation name is 'r16s14', location is LC3_A2, type is buried.
r16s14 = DFFE( d7, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':28' = 'r16s15'
-- Equation name is 'r16s15', location is LC1_A3, type is buried.
r16s15 = DFFE( d8, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
Project Information f:\zztt\vhdl\designtaxi_25\reg16.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,957K
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