duanxuan.rpt

出租车计费器,VHDL实现

         # !_LC1_C8 & !_LC2_B16
         #  _LC2_B4 & !_LC2_B16
         # !_LC1_C8 & !_LC2_B4
         #  _LC1_C8 &  _LC2_B4;

-- Node name is ':1763' 
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = LCELL( _EQ076);
  _EQ076 =  _LC1_A10 &  _LC2_A10
         # !_LC1_A6 &  _LC2_A10 &  _LC4_A10;

-- Node name is ':1767' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ077);
  _EQ077 = !_LC2_A7 &  _LC3_A2
         # !_LC2_A7 &  _LC3_A10
         #  _LC1_A4;

-- Node name is '~1803~1' 
-- Equation name is '~1803~1', location is LC4_A3, type is buried.
-- synthesized logic cell 
_LC4_A3  = LCELL( _EQ078);
  _EQ078 =  _LC1_B4 &  _LC1_C8 & !_LC2_B4
         #  _LC1_C8 & !_LC2_B4 & !_LC2_B16;

-- Node name is ':1815' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ079);
  _EQ079 =  _LC1_A3 &  _LC6_A3
         #  _LC1_A3 &  _LC4_A3
         #  _LC1_A4;

-- Node name is '~1817~1' 
-- Equation name is '~1817~1', location is LC1_A3, type is buried.
-- synthesized logic cell 
_LC1_A3  = LCELL( _EQ080);
  _EQ080 =  _LC1_C8
         #  _LC1_B4
         # !_LC2_B4 & !_LC2_B16;

-- Node name is '~1839~1' 
-- Equation name is '~1839~1', location is LC2_A3, type is buried.
-- synthesized logic cell 
_LC2_A3  = LCELL( _EQ081);
  _EQ081 =  _LC1_B4 & !_LC1_C8 & !_LC2_B4
         #  _LC1_B4 & !_LC1_C8 & !_LC2_B16;

-- Node name is '~1857~1' 
-- Equation name is '~1857~1', location is LC2_A1, type is buried.
-- synthesized logic cell 
_LC2_A1  = LCELL( _EQ082);
  _EQ082 = !_LC1_B4 &  _LC1_C8 & !_LC2_B4 & !_LC2_B16
         # !_LC1_B4 & !_LC1_C8 &  _LC2_B4;

-- Node name is '~1865~1' 
-- Equation name is '~1865~1', location is LC1_B12, type is buried.
-- synthesized logic cell 
_LC1_B12 = LCELL( _EQ083);
  _EQ083 = !sec4 &  sec5 &  sec6 &  sec7;

-- Node name is '~1865~2' 
-- Equation name is '~1865~2', location is LC1_C9, type is buried.
-- synthesized logic cell 
_LC1_C9  = LCELL( _EQ084);
  _EQ084 =  _LC1_C6 & !_LC3_A13 & !_LC5_A13 &  strpri2;

-- Node name is '~1865~3' 
-- Equation name is '~1865~3', location is LC1_C5, type is buried.
-- synthesized logic cell 
_LC1_C5  = LCELL( _EQ085);
  _EQ085 =  _LC1_B12 & !start
         #  _LC1_C9 &  _LC6_C5;

-- Node name is '~1865~4' 
-- Equation name is '~1865~4', location is LC4_B6, type is buried.
-- synthesized logic cell 
_LC4_B6  = LCELL( _EQ086);
  _EQ086 =  sec1 &  sec2 &  sec3 & !start;

-- Node name is '~1865~5' 
-- Equation name is '~1865~5', location is LC3_B6, type is buried.
-- synthesized logic cell 
_LC3_B6  = LCELL( _EQ087);
  _EQ087 =  _LC1_C5 &  _LC2_A14
         # !_LC1_B18 & !_LC2_A14 &  _LC4_B6;

-- Node name is '~1865~6' 
-- Equation name is '~1865~6', location is LC4_C12, type is buried.
-- synthesized logic cell 
_LC4_C12 = LCELL( _EQ088);
  _EQ088 =  _LC1_C6 & !_LC2_A13 &  _LC3_B6 & !_LC5_A13;

-- Node name is '~1865~7' 
-- Equation name is '~1865~7', location is LC3_C12, type is buried.
-- synthesized logic cell 
_LC3_C12 = LCELL( _EQ089);
  _EQ089 = !strpri0 &  strpri1 &  strpri3;

-- Node name is '~1865~8' 
-- Equation name is '~1865~8', location is LC1_C12, type is buried.
-- synthesized logic cell 
_LC1_C12 = LCELL( _EQ090);
  _EQ090 =  _LC1_C9 & !_LC2_A13 &  _LC3_C12 & !_LC5_A13;

-- Node name is '~1865~9' 
-- Equation name is '~1865~9', location is LC4_B11, type is buried.
-- synthesized logic cell 
_LC4_B11 = LCELL( _EQ091);
  _EQ091 = !min0 &  min1 &  min2;

-- Node name is '~1865~10' 
-- Equation name is '~1865~10', location is LC1_B11, type is buried.
-- synthesized logic cell 
_LC1_B11 = LCELL( _EQ092);
  _EQ092 =  _LC2_A13 &  _LC4_B11 &  min3
         #  _LC1_A14 & !_LC2_A13;

-- Node name is '~1865~11' 
-- Equation name is '~1865~11', location is LC2_B10, type is buried.
-- synthesized logic cell 
_LC2_B10 = LCELL( _EQ093);
  _EQ093 =  _LC6_B10 & !min4 &  min5 &  min6;

-- Node name is '~1865~12' 
-- Equation name is '~1865~12', location is LC3_B10, type is buried.
-- synthesized logic cell 
_LC3_B10 = LCELL( _EQ094);
  _EQ094 =  _LC1_B11 & !_LC5_A13 & !_LC7_A13
         #  _LC2_B10 & !_LC7_A13;

-- Node name is '~1865~13' 
-- Equation name is '~1865~13', location is LC4_B10, type is buried.
-- synthesized logic cell 
_LC4_B10 = LCELL( _EQ095);
  _EQ095 = !fare0 &  fare1 &  fare2 &  _LC8_B10;

-- Node name is '~1865~14' 
-- Equation name is '~1865~14', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ096);
  _EQ096 = !fare4 &  fare5 &  fare6 &  _LC4_B4;

-- Node name is '~1865~15' 
-- Equation name is '~1865~15', location is LC1_B10, type is buried.
-- synthesized logic cell 
_LC1_B10 = LCELL( _EQ097);
  _EQ097 =  _LC3_B10 & !_LC6_A13
         #  _LC4_B10 & !_LC6_A13
         #  _LC3_B4;

-- Node name is '~1865~16' 
-- Equation name is '~1865~16', location is LC7_C5, type is buried.
-- synthesized logic cell 
_LC7_C5  = LCELL( _EQ098);
  _EQ098 =  _LC1_C9 &  _LC6_C5;

-- Node name is '~1865~17' 
-- Equation name is '~1865~17', location is LC2_C5, type is buried.
-- synthesized logic cell 
_LC2_C5  = LCELL( _EQ099);
  _EQ099 = !_LC2_A13 &  _LC7_C5 &  strpri1
         # !_LC2_A13 &  _LC2_A14 &  _LC7_C5;

-- Node name is '~1865~18' 
-- Equation name is '~1865~18', location is LC1_C10, type is buried.
-- synthesized logic cell 
_LC1_C10 = LCELL( _EQ100);
  _EQ100 =  _LC6_A13 &  start
         #  _LC1_C6 &  _LC3_A13;

-- Node name is '~1865~19' 
-- Equation name is '~1865~19', location is LC6_C12, type is buried.
-- synthesized logic cell 
_LC6_C12 = LCELL( _EQ101);
  _EQ101 =  _LC1_C10 &  _LC2_C5
         #  _LC1_C10 & !_LC6_A13 & !start;

-- Node name is '~1865~20' 
-- Equation name is '~1865~20', location is LC5_C12, type is buried.
-- synthesized logic cell 
_LC5_C12 = LCELL( _EQ102);
  _EQ102 =  _LC1_B10 &  _LC1_C12
         #  _LC1_B10 & !start
         #  _LC6_C12;

-- Node name is '~1865~21' 
-- Equation name is '~1865~21', location is LC6_C15, type is buried.
-- synthesized logic cell 
_LC6_C15 = LCELL( _EQ103);
  _EQ103 = !_LC1_A14 & !_LC2_A13;

-- Node name is '~1865~22' 
-- Equation name is '~1865~22', location is LC5_C15, type is buried.
-- synthesized logic cell 
_LC5_C15 = LCELL( _EQ104);
  _EQ104 =  _LC2_A13 & !strpri4 &  strpri5
         #  _LC2_A14;

-- Node name is '~1865~23' 
-- Equation name is '~1865~23', location is LC3_C15, type is buried.
-- synthesized logic cell 
_LC3_C15 = LCELL( _EQ105);
  _EQ105 =  _LC6_C15 & !_LC7_C15 &  unipri1
         #  _LC5_C15;

-- Node name is '~1865~24' 
-- Equation name is '~1865~24', location is LC2_C15, type is buried.
-- synthesized logic cell 
_LC2_C15 = LCELL( _EQ106);
  _EQ106 =  _LC1_A14 & !_LC2_A13 & !strpri0 &  strpri1;

-- Node name is '~1865~25' 
-- Equation name is '~1865~25', location is LC4_C15, type is buried.
-- synthesized logic cell 
_LC4_C15 = LCELL( _EQ107);
  _EQ107 =  _LC3_C15 &  start
         #  _LC2_C15 & !_LC6_A13;

-- Node name is '~1865~26' 
-- Equation name is '~1865~26', location is LC4_C19, type is buried.
-- synthesized logic cell 
_LC4_C19 = LCELL( _EQ108);
  _EQ108 =  _LC4_C15 & !_LC5_A13 & !_LC7_A13;

-- Node name is '~1865~27' 
-- Equation name is '~1865~27', location is LC6_C7, type is buried.
-- synthesized logic cell 
_LC6_C7  = LCELL( _EQ109);
  _EQ109 =  _LC1_C11 & !_LC2_A13
         #  _LC2_A13 &  strpri6 &  strpri7;

-- Node name is '~1865~28' 
-- Equation name is '~1865~28', location is LC5_C7, type is buried.
-- synthesized logic cell 
_LC5_C7  = LCELL( _EQ110);
  _EQ110 =  _LC1_C6 &  _LC2_A14 &  _LC2_C7
         #  _LC1_C6 &  _LC2_C7 &  _LC6_C7;

-- Node name is '~1865~29' 
-- Equation name is '~1865~29', location is LC1_C7, type is buried.
-- synthesized logic cell 
_LC1_C7  = LCELL( _EQ111);
  _EQ111 =  _LC4_C19 &  _LC5_C7
         #  _LC1_C10 &  _LC5_C7 &  _LC8_C7;

-- Node name is '~1865~30' 
-- Equation name is '~1865~30', location is LC2_C12, type is buried.
-- synthesized logic cell 
_LC2_C12 = LCELL( _EQ112);
  _EQ112 =  _LC2_A3
         #  _LC4_C12
         #  _LC5_C12
         #  _LC1_C7;

-- Node name is '~1865~31' 
-- Equation name is '~1865~31', location is LC3_A1, type is buried.
-- synthesized logic cell 
_LC3_A1  = LCELL( _EQ113);
  _EQ113 = !_LC1_A6 &  _LC6_A1
         # !_LC1_A6 &  _LC4_A1
         # !_LC1_A6 &  _LC2_C12;

-- Node name is '~1865~32' 
-- Equation name is '~1865~32', location is LC1_A12, type is buried.
-- synthesized logic cell 
_LC1_A12 = LCELL( _EQ114);
  _EQ114 = !_LC1_A4 & !_LC2_A7;

-- Node name is ':1865' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ115);
  _EQ115 =  _LC1_A12 &  _LC3_A1
         #  _LC1_A12 &  _LC2_A1
         #  _LC1_A12 & !_LC4_A11;



Project Information                    f:\zztt\vhdl\designtaxi_25\duanxuan.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 21,941K