📄 duanxuan.rpt
字号:
- 1 - B 16 OR2 ! 1 2 0 1 :1006
- 1 - B 04 OR2 ! 1 3 0 20 :1022
- 1 - C 08 OR2 1 3 0 20 :1028
- 1 - C 06 OR2 s ! 0 2 0 7 ~1029~1
- 2 - B 04 OR2 1 2 0 20 :1034
- 2 - B 16 OR2 ! 1 3 0 20 :1040
- 4 - A 01 AND2 0 4 0 1 :1428
- 3 - A 03 AND2 0 4 0 1 :1440
- 1 - A 06 OR2 ! 0 4 0 3 :1488
- 1 - A 10 AND2 0 4 0 1 :1500
- 6 - A 03 OR2 0 4 0 1 :1515
- 3 - A 02 AND2 0 4 0 2 :1548
- 2 - A 07 OR2 ! 0 4 0 3 :1560
- 1 - A 04 OR2 ! 0 4 0 4 :1572
- 7 - A 09 OR2 0 4 1 0 :1575
- 6 - A 01 OR2 0 4 0 1 :1590
- 4 - A 11 OR2 s ! 0 4 0 2 ~1613~1
- 5 - A 01 OR2 0 4 0 1 :1613
- 7 - A 01 OR2 0 4 1 0 :1623
- 2 - A 02 OR2 s 0 4 0 1 ~1662~1
- 1 - A 02 OR2 s 0 4 0 1 ~1662~2
- 5 - A 02 OR2 0 4 1 0 :1671
- 1 - A 08 OR2 0 4 1 0 :1719
- 4 - A 10 OR2 0 4 0 1 :1743
- 2 - A 10 OR2 s 0 4 0 1 ~1763~1
- 3 - A 10 OR2 0 4 0 1 :1763
- 7 - A 02 OR2 0 4 1 0 :1767
- 4 - A 03 OR2 s 0 4 0 1 ~1803~1
- 5 - A 03 OR2 0 4 1 0 :1815
- 1 - A 03 OR2 s 0 4 0 1 ~1817~1
- 2 - A 03 OR2 s 0 4 0 2 ~1839~1
- 2 - A 01 OR2 s 0 4 0 2 ~1857~1
- 1 - B 12 AND2 s 4 0 0 1 ~1865~1
- 1 - C 09 AND2 s 1 3 0 3 ~1865~2
- 1 - C 05 OR2 s 1 3 0 1 ~1865~3
- 4 - B 06 AND2 s 4 0 0 1 ~1865~4
- 3 - B 06 OR2 s 0 4 0 1 ~1865~5
- 4 - C 12 AND2 s 0 4 0 1 ~1865~6
- 3 - C 12 AND2 s 3 0 0 1 ~1865~7
- 1 - C 12 AND2 s 0 4 0 1 ~1865~8
- 4 - B 11 AND2 s 3 0 0 1 ~1865~9
- 1 - B 11 OR2 s 1 3 0 1 ~1865~10
- 2 - B 10 AND2 s 3 1 0 1 ~1865~11
- 3 - B 10 OR2 s 0 4 0 1 ~1865~12
- 4 - B 10 AND2 s 3 1 0 1 ~1865~13
- 3 - B 04 AND2 s 3 1 0 1 ~1865~14
- 1 - B 10 OR2 s 0 4 0 1 ~1865~15
- 7 - C 05 AND2 s 0 2 0 1 ~1865~16
- 2 - C 05 OR2 s 1 3 0 1 ~1865~17
- 1 - C 10 OR2 s 1 3 0 2 ~1865~18
- 6 - C 12 OR2 s 1 3 0 1 ~1865~19
- 5 - C 12 OR2 s 1 3 0 1 ~1865~20
- 6 - C 15 AND2 s 0 2 0 1 ~1865~21
- 5 - C 15 OR2 s 2 2 0 1 ~1865~22
- 3 - C 15 OR2 s 1 3 0 1 ~1865~23
- 2 - C 15 AND2 s 2 2 0 1 ~1865~24
- 4 - C 15 OR2 s 1 3 0 1 ~1865~25
- 4 - C 19 AND2 s 0 3 0 1 ~1865~26
- 6 - C 07 OR2 s 2 2 0 1 ~1865~27
- 5 - C 07 OR2 s 0 4 0 1 ~1865~28
- 1 - C 07 OR2 s 0 4 0 1 ~1865~29
- 2 - C 12 OR2 s 0 4 0 1 ~1865~30
- 3 - A 01 OR2 s 0 4 0 1 ~1865~31
- 1 - A 12 AND2 s 0 2 0 2 ~1865~32
- 1 - A 01 OR2 0 4 1 0 :1865
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 14/ 96( 14%) 11/ 48( 22%) 1/ 48( 2%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
B: 18/ 96( 18%) 19/ 48( 39%) 2/ 48( 4%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
C: 17/ 96( 17%) 13/ 48( 27%) 1/ 48( 2%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** EQUATIONS **
fare0 : INPUT;
fare1 : INPUT;
fare2 : INPUT;
fare3 : INPUT;
fare4 : INPUT;
fare5 : INPUT;
fare6 : INPUT;
fare7 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
min7 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
sec7 : INPUT;
start : INPUT;
strpri0 : INPUT;
strpri1 : INPUT;
strpri2 : INPUT;
strpri3 : INPUT;
strpri4 : INPUT;
strpri5 : INPUT;
strpri6 : INPUT;
strpri7 : INPUT;
unipri0 : INPUT;
unipri1 : INPUT;
wei80 : INPUT;
wei81 : INPUT;
wei82 : INPUT;
wei83 : INPUT;
wei84 : INPUT;
wei85 : INPUT;
wei86 : INPUT;
wei87 : INPUT;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC1_A1;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC5_A3;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = _LC7_A2;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC1_A8;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC5_A2;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC7_A1;
-- Node name is 'seg6'
-- Equation name is 'seg6', type is output
seg6 = _LC7_A9;
-- Node name is '~302~1'
-- Equation name is '~302~1', location is LC2_A17, type is buried.
-- synthesized logic cell
_LC2_A17 = LCELL( _EQ001);
_EQ001 = !wei85 & !wei86 & !wei87;
-- Node name is '~302~2'
-- Equation name is '~302~2', location is LC3_A14, type is buried.
-- synthesized logic cell
_LC3_A14 = LCELL( _EQ002);
_EQ002 = _LC2_A17 & !wei83 & !wei84;
-- Node name is ':302'
-- Equation name is '_LC6_A14', type is buried
!_LC6_A14 = _LC6_A14~NOT;
_LC6_A14~NOT = LCELL( _EQ003);
_EQ003 = wei81
# !wei80
# !_LC3_A14
# wei82;
-- Node name is ':322'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ004);
_EQ004 = _LC3_A14 & !wei80 & !wei81 & wei82;
-- Node name is ':326'
-- Equation name is '_LC6_C5', type is buried
!_LC6_C5 = _LC6_C5~NOT;
_LC6_C5~NOT = LCELL( _EQ005);
_EQ005 = !strpri3
# !_LC1_A14;
-- Node name is ':327'
-- Equation name is '_LC1_C11', type is buried
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ006);
_EQ006 = _LC6_A14
# _LC1_A14;
-- Node name is ':342'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ007);
_EQ007 = !_LC1_A13 & _LC2_A17 & wei83 & !wei84;
-- Node name is ':346'
-- Equation name is '_LC3_C5', type is buried
!_LC3_C5 = _LC3_C5~NOT;
_LC3_C5~NOT = LCELL( _EQ008);
_EQ008 = !strpri7
# !_LC2_A13;
-- Node name is ':347'
-- Equation name is '_LC4_C5', type is buried
!_LC4_C5 = _LC4_C5~NOT;
_LC4_C5~NOT = LCELL( _EQ009);
_EQ009 = !_LC1_C11 & !_LC6_C5
# _LC2_A13;
-- Node name is ':362'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ010);
_EQ010 = _LC3_A14 & !wei80 & wei81 & !wei82;
-- Node name is ':382'
-- Equation name is '_LC5_A13', type is buried
!_LC5_A13 = _LC5_A13~NOT;
_LC5_A13~NOT = LCELL( _EQ011);
_EQ011 = !_LC2_A17
# !wei84
# wei83
# _LC1_A13;
-- Node name is ':402'
-- Equation name is '_LC3_A13', type is buried
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ012);
_EQ012 = wei87
# wei86
# _LC4_A13
# !wei85;
-- Node name is ':422'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ013);
_EQ013 = !_LC4_A13 & !wei85 & wei86 & !wei87;
-- Node name is '~442~1'
-- Equation name is '~442~1', location is LC1_A13, type is buried.
-- synthesized logic cell
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ014);
_EQ014 = !wei80 & !wei81 & !wei82;
-- Node name is '~442~2'
-- Equation name is '~442~2', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( _EQ015);
_EQ015 = wei83
# _LC1_A13
# wei84;
-- Node name is ':442'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ016);
_EQ016 = !_LC4_A13 & !wei85 & !wei86 & wei87;
-- Node name is '~445~1'
-- Equation name is '~445~1', location is LC2_C7, type is buried.
-- synthesized logic cell
_LC2_C7 = LCELL( _EQ017);
_EQ017 = !_LC3_A13 & !_LC5_A13;
-- Node name is '~445~2'
-- Equation name is '~445~2', location is LC3_C7, type is buried.
-- synthesized logic cell
_LC3_C7 = LCELL( _EQ018);
_EQ018 = !_LC2_A14 & _LC2_C7;
-- Node name is ':445'
-- Equation name is '_LC5_C5', type is buried
!_LC5_C5 = _LC5_C5~NOT;
_LC5_C5~NOT = LCELL( _EQ019);
_EQ019 = _LC1_C6 & !_LC3_C5 & _LC3_C7 & !_LC4_C5;
-- Node name is ':454'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ020);
_EQ020 = _LC1_A14 & strpri2
# _LC1_C11;
-- Node name is ':466'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ021);
_EQ021 = !_LC2_A13 & _LC2_C8
# _LC2_A13 & strpri6
# !_LC3_C7;
-- Node name is ':481'
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = LCELL( _EQ022);
_EQ022 = !_LC1_A14 & !_LC6_A14
# !_LC1_A14 & unipri1
# _LC1_A14 & strpri1;
-- Node name is ':487'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ023);
_EQ023 = !_LC2_A13 & _LC7_C7
# _LC2_A14
# _LC2_A13 & strpri5;
-- Node name is ':499'
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = LCELL( _EQ024);
_EQ024 = !_LC1_C6
# _LC2_C7 & _LC8_C7;
-- Node name is ':505'
-- Equation name is '_LC7_C15', type is buried
!_LC7_C15 = _LC7_C15~NOT;
_LC7_C15~NOT = LCELL( _EQ025);
_EQ025 = _LC6_A14 & !unipri0;
-- Node name is ':508'
-- Equation name is '_LC8_C15', type is buried
!_LC8_C15 = _LC8_C15~NOT;
_LC8_C15~NOT = LCELL( _EQ026);
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