📄 duanxuan.rpt
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Project Information f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
MAX+plus II Compiler Report File
Version 9.3 7/23/1999
Compiled: 05/25/2005 16:35:45
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DUANXUAN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
duanxuan EPF10K10LC84-3 43 7 0 0 0 % 115 19 %
User Pins: 43 7 0
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
***** Logic for device 'duanxuan' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** ERROR SUMMARY **
Info: Chip 'duanxuan' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R R R O
E s E E N
V S t G S S F
f f C E r s N E E _ ^
a s a m s s m C R p s t s D R s R s # D n
r e r i e e i I V r e a e I V e V e T O C
e c e n c c n N E i c r c N E g E g C N E
2 2 1 7 1 3 6 T D 1 7 t 0 T D 2 D 4 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | wei80
^nCE | 14 72 | wei81
#TDI | 15 71 | wei82
wei85 | 16 70 | wei83
wei86 | 17 69 | wei84
wei87 | 18 68 | GNDINT
seg6 | 19 67 | sec5
VCCINT | 20 66 | sec4
min3 | 21 65 | min5
min1 | 22 EPF10K10LC84-3 64 | min4
min0 | 23 63 | VCCINT
fare6 | 24 62 | strpri2
fare4 | 25 61 | strpri3
GNDINT | 26 60 | strpri5
unipri1 | 27 59 | strpri6
strpri4 | 28 58 | strpri7
unipri0 | 29 57 | #TMS
seg5 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | seg3
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ m f f R f V G s s f V G s R R R s R R
C n i a a E a C N e t a C N e E E E e E E
C C n r r S r C D c r r C D g S S S g S S
I O 2 e e E e I I 6 p e I I 0 E E E 1 E E
N N 7 5 R 3 N N r 0 N N R R R R R
T F V T T i T T V V V V V
I E 0 E E E E E
G D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
A2 5/ 8( 62%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
A3 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A8 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A10 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A13 7/ 8( 87%) 5/ 8( 62%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
A14 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B4 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
B6 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
B10 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
B11 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
B12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B16 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C5 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
C6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C7 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
C8 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C12 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
C15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 44/53 ( 83%)
Total logic cells used: 115/576 ( 19%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 413/2304 ( 17%)
Total input pins required: 43
Total input I/O cell registers required: 0
Total output pins required: 7
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 115
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 50/ 576 ( 8%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 5 6 1 0 1 1 1 1 4 1 1 0 7 4 0 0 1 0 0 0 0 0 0 0 41/0
B: 0 0 0 7 0 6 0 0 0 8 7 1 0 0 0 0 7 0 1 0 0 0 0 0 0 37/0
C: 0 0 0 0 7 1 8 3 1 1 1 6 0 0 0 8 0 0 0 1 0 0 0 0 0 37/0
Total: 7 5 6 8 7 8 9 4 2 13 9 8 0 7 4 8 7 1 1 1 0 0 0 0 0 115/0
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 2 fare0
9 - - - 02 INPUT 0 0 0 2 fare1
11 - - - 01 INPUT 0 0 0 2 fare2
39 - - - 11 INPUT 0 0 0 1 fare3
25 - - B -- INPUT 0 0 0 2 fare4
37 - - - 09 INPUT 0 0 0 2 fare5
24 - - B -- INPUT 0 0 0 2 fare6
36 - - - 07 INPUT 0 0 0 1 fare7
23 - - B -- INPUT 0 0 0 2 min0
22 - - B -- INPUT 0 0 0 2 min1
35 - - - 06 INPUT 0 0 0 2 min2
21 - - B -- INPUT 0 0 0 2 min3
64 - - B -- INPUT 0 0 0 2 min4
65 - - B -- INPUT 0 0 0 2 min5
5 - - - 05 INPUT 0 0 0 2 min6
8 - - - 03 INPUT 0 0 0 1 min7
83 - - - 13 INPUT 0 0 0 1 sec0
7 - - - 03 INPUT 0 0 0 2 sec1
10 - - - 01 INPUT 0 0 0 2 sec2
6 - - - 04 INPUT 0 0 0 2 sec3
66 - - B -- INPUT 0 0 0 2 sec4
67 - - B -- INPUT 0 0 0 2 sec5
42 - - - -- INPUT 0 0 0 2 sec6
1 - - - -- INPUT 0 0 0 2 sec7
84 - - - -- INPUT 0 0 0 10 start
43 - - - -- INPUT 0 0 0 3 strpri0
2 - - - -- INPUT 0 0 0 4 strpri1
62 - - C -- INPUT 0 0 0 2 strpri2
61 - - C -- INPUT 0 0 0 2 strpri3
28 - - C -- INPUT 0 0 0 2 strpri4
60 - - C -- INPUT 0 0 0 2 strpri5
59 - - C -- INPUT 0 0 0 2 strpri6
58 - - C -- INPUT 0 0 0 2 strpri7
29 - - C -- INPUT 0 0 0 1 unipri0
27 - - C -- INPUT 0 0 0 2 unipri1
73 - - A -- INPUT 0 0 0 4 wei80
72 - - A -- INPUT 0 0 0 4 wei81
71 - - A -- INPUT 0 0 0 4 wei82
70 - - A -- INPUT 0 0 0 4 wei83
69 - - A -- INPUT 0 0 0 4 wei84
16 - - A -- INPUT 0 0 0 4 wei85
17 - - A -- INPUT 0 0 0 4 wei86
18 - - A -- INPUT 0 0 0 4 wei87
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
47 - - - 14 OUTPUT 0 1 0 0 seg0
51 - - - 18 OUTPUT 0 1 0 0 seg1
80 - - - 23 OUTPUT 0 1 0 0 seg2
54 - - - 21 OUTPUT 0 1 0 0 seg3
78 - - - 24 OUTPUT 0 1 0 0 seg4
30 - - C -- OUTPUT 0 1 0 0 seg5
19 - - A -- OUTPUT 0 1 0 0 seg6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\duanxuan.rpt
duanxuan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 17 AND2 s 3 0 0 3 ~302~1
- 3 - A 14 AND2 s 2 1 0 3 ~302~2
- 6 - A 14 OR2 ! 3 1 0 7 :302
- 1 - A 14 AND2 3 1 0 12 :322
- 6 - C 05 OR2 ! 1 1 0 3 :326
- 1 - C 11 OR2 ! 0 2 0 3 :327
- 2 - A 13 AND2 2 2 0 17 :342
- 3 - C 05 OR2 ! 1 1 0 1 :346
- 4 - C 05 OR2 ! 0 3 0 1 :347
- 2 - A 14 AND2 3 1 0 11 :362
- 5 - A 13 OR2 ! 2 2 0 12 :382
- 3 - A 13 OR2 ! 3 1 0 8 :402
- 7 - A 13 AND2 3 1 0 9 :422
- 1 - A 13 AND2 s ! 3 0 0 3 ~442~1
- 4 - A 13 OR2 s 2 1 0 3 ~442~2
- 6 - A 13 AND2 3 1 0 11 :442
- 2 - C 07 AND2 s 0 2 0 3 ~445~1
- 3 - C 07 AND2 s 0 2 0 2 ~445~2
- 5 - C 05 AND2 ! 0 4 0 1 :445
- 2 - C 08 OR2 1 2 0 1 :454
- 3 - C 08 OR2 1 3 0 1 :466
- 7 - C 07 OR2 2 2 0 1 :481
- 8 - C 07 OR2 1 3 0 2 :487
- 4 - C 07 OR2 0 3 0 1 :499
- 7 - C 15 AND2 ! 1 1 0 2 :505
- 8 - C 15 OR2 ! 1 2 0 1 :508
- 1 - C 15 OR2 ! 1 3 0 1 :519
- 7 - B 16 OR2 ! 0 4 0 1 :523
- 6 - B 06 OR2 s 2 2 0 1 ~825~1
- 1 - B 06 OR2 ! 1 3 0 1 :845
- 6 - B 10 OR2 ! 1 1 0 2 :866
- 7 - B 10 OR2 ! 0 4 0 1 :885
- 8 - B 10 OR2 ! 1 1 0 2 :906
- 4 - B 04 OR2 ! 1 1 0 2 :926
- 5 - B 10 OR2 ! 0 4 0 1 :927
- 2 - B 11 OR2 s 2 2 0 1 ~937~1
- 7 - B 11 OR2 1 3 0 1 :940
- 6 - B 11 OR2 1 3 0 1 :946
- 5 - B 11 OR2 1 2 0 1 :949
- 3 - B 11 OR2 1 2 0 1 :952
- 5 - B 06 OR2 s ! 2 2 0 1 ~964~1
- 2 - B 06 OR2 1 3 0 1 :967
- 7 - B 04 OR2 1 3 0 1 :973
- 6 - B 04 OR2 1 2 0 1 :976
- 5 - B 04 OR2 1 2 0 1 :979
- 1 - B 18 AND2 ! 1 1 0 2 :985
- 6 - B 16 OR2 ! 1 2 0 1 :988
- 5 - B 16 OR2 ! 1 3 0 1 :994
- 4 - B 16 OR2 ! 1 2 0 1 :997
- 3 - B 16 OR2 ! 1 3 0 1 :1003
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