vtbird.rpt

雷鸟车尾灯状态机,vhdl实现

_LC3_A12~NOT = LCELL( _EQ017);
  _EQ017 = !_LC3_A4
         # !_LC1_B1
         # !_LC5_A3
         # !_LC1_A1;

-- Node name is ':727' 
-- Equation name is '_LC1_A7', type is buried 
!_LC1_A7 = _LC1_A7~NOT;
_LC1_A7~NOT = LCELL( _EQ018);
  _EQ018 =  _LC3_A4
         # !_LC1_A1
         # !_LC1_B1
         # !_LC5_A3;

-- Node name is ':743' 
-- Equation name is '_LC3_A5', type is buried 
!_LC3_A5 = _LC3_A5~NOT;
_LC3_A5~NOT = LCELL( _EQ019);
  _EQ019 = !_LC1_B1
         #  _LC5_A3
         #  _LC3_A4
         # !_LC1_A1;

-- Node name is '~746~1' 
-- Equation name is '~746~1', location is LC1_A13, type is buried.
-- synthesized logic cell 
_LC1_A13 = LCELL( _EQ020);
  _EQ020 =  _LC3_A5
         #  _LC1_A7;

-- Node name is ':746' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ021);
  _EQ021 = !_LC3_A12 &  _LC6_A4
         #  _LC1_A11 & !_LC3_A12
         #  _LC1_A13;

-- Node name is '~759~1' 
-- Equation name is '~759~1', location is LC1_A1, type is buried.
-- synthesized logic cell 
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ022);
  _EQ022 =  _LC7_B1
         #  _LC7_A3
         #  _LC2_B1;

-- Node name is ':759' 
-- Equation name is '_LC1_A6', type is buried 
!_LC1_A6 = _LC1_A6~NOT;
_LC1_A6~NOT = LCELL( _EQ023);
  _EQ023 =  _LC1_B1
         #  _LC5_A3
         #  _LC3_A4
         # !_LC1_A1;

-- Node name is ':779' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = LCELL( _EQ024);
  _EQ024 = !_LC1_A9 & !_LC2_A8 &  _LC5_A3
         # !_LC1_A9 &  _LC2_A2;

-- Node name is ':786' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = LCELL( _EQ025);
  _EQ025 =  _LC1_A13
         # !_LC3_A12 &  _LC4_A3
         #  _LC1_A11 & !_LC3_A12;

-- Node name is ':790' 
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = LCELL( _EQ026);
  _EQ026 =  _LC1_A6 &  LEFT &  RIGHT
         #  HAZ &  _LC1_A6;

-- Node name is ':801' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = LCELL( _EQ027);
  _EQ027 =  _LC2_A2
         # !_LC2_A8 &  _LC3_A4;

-- Node name is ':812' 
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ028);
  _EQ028 = !_LC1_A9 & !_LC3_A12 &  _LC5_A4
         #  _LC1_A11 & !_LC3_A12;

-- Node name is ':813' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ029);
  _EQ029 = !_LC3_A5 &  _LC4_A4
         #  _LC1_A7 & !_LC3_A5
         #  HAZ &  _LC3_A5;

-- Node name is '~830~1' 
-- Equation name is '~830~1', location is LC4_A8, type is buried.
-- synthesized logic cell 
_LC4_A8  = LCELL( _EQ030);
  _EQ030 =  _LC1_A8 & !_LC2_A8
         # !_LC2_A8 &  _LC4_A10;

-- Node name is ':833' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ031);
  _EQ031 = !_LC1_A9 &  _LC4_A8 &  _LC7_A3
         # !_LC1_A9 &  _LC4_A2;

-- Node name is ':839' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ032);
  _EQ032 = !_LC1_A7 &  _LC1_A11 & !_LC3_A12
         # !_LC1_A7 & !_LC3_A12 &  _LC5_A2;

-- Node name is ':840' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ033);
  _EQ033 =  HAZ &  _LC3_A5
         #  _LC1_A3 & !_LC3_A5
         #  HAZ &  _LC1_A7;

-- Node name is ':858' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ034);
  _EQ034 =  _LC2_B1 &  _LC4_A8
         #  _LC4_A2
         #  _LC1_A9;

-- Node name is ':866' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ035);
  _EQ035 = !_LC1_A7 & !_LC3_A12 &  _LC6_A2;

-- Node name is ':867' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ036);
  _EQ036 =  HAZ &  _LC3_A5
         #  HAZ &  _LC1_A7
         #  _LC1_A2 & !_LC3_A5;

-- Node name is ':885' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ037);
  _EQ037 =  _LC4_A2
         #  _LC1_A9
         #  _LC4_A8 &  _LC7_B1;

-- Node name is ':893' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = LCELL( _EQ038);
  _EQ038 = !_LC1_A7 & !_LC3_A12 &  _LC7_A2;

-- Node name is ':894' 
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ039);
  _EQ039 =  HAZ &  _LC3_A5
         #  HAZ &  _LC1_A7
         #  _LC3_A2 & !_LC3_A5;



Project Information                                  d:\vhdl\vtbird\vtbird.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,541K