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📄 vtbird.rpt

📁 雷鸟车尾灯状态机,vhdl实现
💻 RPT
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字号:

Device-Specific Information:                         d:\vhdl\vtbird\vtbird.rpt
vtbird

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      1     -    B    01       DFFE   +            1    3    1    7  :6
   -      5     -    A    03       DFFE   +            1    3    1    7  :8
   -      3     -    A    04       DFFE   +            1    3    1    7  :10
   -      7     -    A    03       DFFE   +            1    3    1    5  :12
   -      2     -    B    01       DFFE   +            1    3    1    5  :14
   -      7     -    B    01       DFFE   +            1    3    1    5  :16
   -      6     -    B    01        OR2                2    0    0    1  :229
   -      5     -    B    01        OR2                2    0    0    1  :289
   -      1     -    A    08        OR2    s           0    3    0    2  ~647~1
   -      2     -    A    08        OR2        !       0    4    0    4  :647
   -      4     -    A    02       AND2                0    4    0    4  :679
   -      2     -    A    02       AND2                1    1    0    3  :683
   -      4     -    A    10        OR2    s           0    3    0    3  ~695~1
   -      1     -    A    09       AND2                0    4    0    7  :695
   -      1     -    A    11       AND2                1    1    0    4  :699
   -      6     -    A    04        OR2                0    4    0    1  :700
   -      3     -    A    12        OR2        !       0    4    0    6  :711
   -      1     -    A    07        OR2        !       0    4    0    8  :727
   -      3     -    A    05        OR2        !       0    4    0    5  :743
   -      1     -    A    13        OR2    s           0    2    0    2  ~746~1
   -      1     -    A    04        OR2                0    4    0    1  :746
   -      1     -    A    01        OR2    s   !       0    3    0    4  ~759~1
   -      1     -    A    06        OR2        !       0    4    0    7  :759
   -      4     -    A    03        OR2                0    4    0    1  :779
   -      3     -    A    03        OR2                0    4    0    1  :786
   -      3     -    B    01        OR2                3    1    0    4  :790
   -      5     -    A    04        OR2                0    3    0    1  :801
   -      4     -    A    04        OR2                0    4    0    1  :812
   -      2     -    A    04        OR2                1    3    0    1  :813
   -      4     -    A    08        OR2    s           0    3    0    3  ~830~1
   -      5     -    A    02        OR2                0    4    0    1  :833
   -      1     -    A    03        OR2                0    4    0    1  :839
   -      2     -    A    03        OR2                1    3    0    1  :840
   -      6     -    A    02        OR2                0    4    0    1  :858
   -      1     -    A    02       AND2                0    3    0    1  :866
   -      4     -    B    01        OR2                1    3    0    1  :867
   -      7     -    A    02        OR2                0    4    0    1  :885
   -      3     -    A    02       AND2                0    3    0    1  :893
   -      8     -    B    01        OR2                1    3    0    1  :894


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                         d:\vhdl\vtbird\vtbird.rpt
vtbird

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       3/ 96(  3%)    17/ 48( 35%)     0/ 48(  0%)    0/16(  0%)      3/16( 18%)     0/16(  0%)
B:       0/ 96(  0%)     6/ 48( 12%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
02:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         d:\vhdl\vtbird\vtbird.rpt
vtbird

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        6         CLOCK


Device-Specific Information:                         d:\vhdl\vtbird\vtbird.rpt
vtbird

** EQUATIONS **

CLOCK    : INPUT;
HAZ      : INPUT;
LEFT     : INPUT;
RESET    : INPUT;
RIGHT    : INPUT;

-- Node name is 'LIGHTS1' 
-- Equation name is 'LIGHTS1', type is output 
LIGHTS1  =  _LC1_B1;

-- Node name is 'LIGHTS2' 
-- Equation name is 'LIGHTS2', type is output 
LIGHTS2  =  _LC5_A3;

-- Node name is 'LIGHTS3' 
-- Equation name is 'LIGHTS3', type is output 
LIGHTS3  =  _LC3_A4;

-- Node name is 'LIGHTS4' 
-- Equation name is 'LIGHTS4', type is output 
LIGHTS4  =  _LC7_A3;

-- Node name is 'LIGHTS5' 
-- Equation name is 'LIGHTS5', type is output 
LIGHTS5  =  _LC2_B1;

-- Node name is 'LIGHTS6' 
-- Equation name is 'LIGHTS6', type is output 
LIGHTS6  =  _LC7_B1;

-- Node name is ':6' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = DFFE( _EQ001, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ001 =  _LC1_A4 & !_LC1_A6 & !RESET
         #  _LC1_A6 &  _LC6_B1 & !RESET;

-- Node name is ':8' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = DFFE( _EQ002, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ002 = !_LC1_A6 &  _LC3_A3 & !RESET
         #  _LC3_B1 & !RESET;

-- Node name is ':10' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = DFFE( _EQ003, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ003 = !_LC1_A6 &  _LC2_A4 & !RESET
         #  _LC3_B1 & !RESET;

-- Node name is ':12' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = DFFE( _EQ004, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ004 = !_LC1_A6 &  _LC2_A3 & !RESET
         #  _LC3_B1 & !RESET;

-- Node name is ':14' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = DFFE( _EQ005, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ005 =  _LC3_B1 & !RESET
         # !_LC1_A6 &  _LC4_B1 & !RESET;

-- Node name is ':16' 
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = DFFE( _EQ006, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ006 =  _LC1_A6 &  _LC5_B1 & !RESET
         # !_LC1_A6 &  _LC8_B1 & !RESET;

-- Node name is ':229' 
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ007);
  _EQ007 =  LEFT
         #  HAZ;

-- Node name is ':289' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ008);
  _EQ008 =  HAZ
         #  RIGHT;

-- Node name is '~647~1' 
-- Equation name is '~647~1', location is LC1_A8, type is buried.
-- synthesized logic cell 
_LC1_A8  = LCELL( _EQ009);
  _EQ009 = !_LC7_A3
         # !_LC2_B1
         # !_LC7_B1;

-- Node name is ':647' 
-- Equation name is '_LC2_A8', type is buried 
!_LC2_A8 = _LC2_A8~NOT;
_LC2_A8~NOT = LCELL( _EQ010);
  _EQ010 = !_LC3_A4
         # !_LC1_B1
         # !_LC5_A3
         #  _LC1_A8;

-- Node name is ':679' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ011);
  _EQ011 =  _LC2_B1 & !_LC4_A10 & !_LC7_A3 &  _LC7_B1;

-- Node name is ':683' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ012);
  _EQ012 =  HAZ &  _LC4_A2;

-- Node name is '~695~1' 
-- Equation name is '~695~1', location is LC4_A10, type is buried.
-- synthesized logic cell 
_LC4_A10 = LCELL( _EQ013);
  _EQ013 =  _LC1_B1
         #  _LC5_A3
         #  _LC3_A4;

-- Node name is ':695' 
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = LCELL( _EQ014);
  _EQ014 = !_LC2_B1 & !_LC4_A10 & !_LC7_A3 &  _LC7_B1;

-- Node name is ':699' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ015);
  _EQ015 =  HAZ &  _LC1_A9;

-- Node name is ':700' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = LCELL( _EQ016);
  _EQ016 = !_LC1_A9 &  _LC1_B1 & !_LC2_A8
         # !_LC1_A9 &  _LC2_A2;

-- Node name is ':711' 
-- Equation name is '_LC3_A12', type is buried 
!_LC3_A12 = _LC3_A12~NOT;

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