a_run.scr

ip_51core VHDL ALTERA Cyclone II

/* ************************************************************************ */
/* Copyright (c) 1997-2001  Evatronix SA                                    */
/* ************************************************************************ */
/* Please review the terms of the license agreement before using this file. */
/* If you are not an authorised user, please destroy this script file and   */
/* notify Evatronix SA immediately that you inadvertently received an       */
/* unauthorised copy.                                                       */
/* ************************************************************************ */

/* ------------------------------------------------------------------------ */
/* Project name         : C8051                                             */
/* Project description  : C8051 Microcontroller Unit                        */
/* File name            : a_run.scr                                         */
/* File contents        : Top module "C8051" synthesis                      */
/* Purpose              : Master synthesis script                           */
/*                        Sample Script for Synopsys                        */
/* Design Engineer      : M.B.                                              */
/* Version              : 3.01                                              */
/* Last modification    : 2001-10-01                                        */
/* ------------------------------------------------------------------------ */

company = "Evatronix S.A."
top     = "C8051"
module  = "C8051"

/* ------------------------------------------------------------------------ */
/* Directories location                                                     */
/* ------------------------------------------------------------------------ */

work_dir    = "./tools/synopsys/work/"
source_dir  = "./src/core/"
report_dir  = "./tools/synopsys/reports/"
net_dir     = "./tools/synopsys/netlists/"
scripts_dir = "./tools/synopsys/dc_scripts/"

/* ------------------------------------------------------------------------ */
/* Library mapping                                                          */
/* ------------------------------------------------------------------------ */

sh mkdir work_dir
sh mkdir report_dir
sh mkdir net_dir

define_design_lib C8051_lib -path work_dir

/* ------------------------------------------------------------------------ */
/* Analyze utilities package                                                */
/* ------------------------------------------------------------------------ */

analyze -format vhdl -lib C8051_lib {source_dir + "utility.vhd"}

/* ------------------------------------------------------------------------ */
/* Analyze, Elaborate and Optimalize design components file                 */
/* ------------------------------------------------------------------------ */

include scripts_dir + "alu.scr"
include scripts_dir + "clkctrl.scr"
include scripts_dir + "cpu.scr"
include scripts_dir + "isr.scr"
include scripts_dir + "memctrl.scr"
include scripts_dir + "oci.scr"
include scripts_dir + "ports.scr"
include scripts_dir + "ramsfrctrl.scr"
include scripts_dir + "serial.scr"
include scripts_dir + "timer.scr"

/* ------------------------------------------------------------------------ */
/* Analyze, Elaborate and Optimize design file                              */
/* ------------------------------------------------------------------------ */

include scripts_dir + "c8051.scr"

/* ------------------------------------------------------------------------ */
/* Write out the design to a DB file                                        */
/* ------------------------------------------------------------------------ */

write -format db -hierarchy -output work_dir + top + ".db"

/* ------------------------------------------------------------------------ */
/* Write the design report files                                            */
/* ------------------------------------------------------------------------ */

report_area > report_dir + top + ".rep"
report_cell >> report_dir + top + ".rep"
report_timing >> report_dir + top + ".rep"

/* ------------------------------------------------------------------------ */
/* Save design in EDIF format                                               */
/* ------------------------------------------------------------------------ */

write -format edif -hierarchy -output net_dir + top + ".edf"

/* ------------------------------------------------------------------------ */
/* Save design in VHDL format                                               */
/* ------------------------------------------------------------------------ */

write -format vhdl -hierarchy -output net_dir + top + ".vhd"

/* ------------------------------------------------------------------------ */
/* Flatten the design's hierarchy to rationalize netlist constraints files  */
/* ------------------------------------------------------------------------ */

/* ungroup -all -flatten */

/* ------------------------------------------------------------------------ */
/* Write-out the timing constraints that were applied earlier               */
/* ------------------------------------------------------------------------ */

write_script > report_dir + module + ".dc"

/* ------------------------------------------------------------------------ */
/* Exit the Compiler                                                        */
/* ------------------------------------------------------------------------ */

exit

/* ************************************************************************ */