📄 drx3973d.lst
字号:
1074 3 demod->myDemodFunct->typeId = DRX3973D_TYPE_ID;
1075 3 break;
1076 3 case 4 :
1077 3 demod->myDemodFunct->typeId = DRX3974D_TYPE_ID;
1078 3 break;
1079 3 case 5 :
1080 3 demod->myDemodFunct->typeId = DRX3975D_TYPE_ID;
1081 3 break;
1082 3 case 6 :
1083 3 demod->myDemodFunct->typeId = DRX3976D_TYPE_ID;
1084 3 break;
1085 3 case 7 :
1086 3 demod->myDemodFunct->typeId = DRX3977D_TYPE_ID;
1087 3 break;
1088 3 case 8 :
1089 3 demod->myDemodFunct->typeId = DRX3978D_TYPE_ID;
1090 3 break;
1091 3 default:
1092 3 demod->myDemodFunct->typeId = 0;
1093 3 status = DRX_STS_ERROR;
1094 3 break;
1095 3 } /* switch */
1096 2 } /* if */
1097 1
1098 1 return (status);
1099 1
1100 1 rw_error:
1101 1 return (DRX_STS_ERROR);
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 19
1102 1 }
1103
1104
1105
1106 /*============================================================================*/
1107
1108 /**
1109 * \fn DRXStatus_t InitCC( const pDRXDemodInstance_t demod )
1110 * \brief Initialize clock controler
1111 * \param demod pointer to demod data.
1112 * \return DRXStatus_t Return status.
1113 * \retval DRX_STS_OK Success.
1114 * \retval DRX_STS_ERROR Failure.
1115 *
1116 * Two pads are available for clock input.
1117 * Only one pad is bounded to XI and XO pins.
1118 * Both pads can form, together with an external Xtal, an Xtal oscillator.
1119 * One pad can do this with an Xtal from 4 upto 20 MHz. This is prefered.
1120 * Another pad can do this with an Xtal of 48 Mhz. This needs different bounding
1121 * and a metal change. Only needed if to other solution fails.
1122 * Both pads can accept a signal from an external oscillator from at least 4 MHz
1123 * upto 48 MHz.
1124 */
1125 static DRXStatus_t
1126 InitCC( const pDRXDemodInstance_t demod )
1127 {
1128 1 const DRXFrequency_t divider_base = 4000;
1129 1 u16_t divider = 0;
1130 1 #ifndef COMPILE_FOR_QT
1131 1 pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr;
1132 1 #endif
1133 1 DRXFrequency_t oscFreq = demod->myCommonAttr->oscClockFreq;
1134 1 pDRX3973DData_t extAttr= (pDRX3973DData_t) demod -> myExtAttr;
1135 1
1136 1 /* compute clock divider */
1137 1 divider = (u16_t) (oscFreq/divider_base);
1138 1
1139 1 /* handle non 4-fold clocks, asymetric tolerance range:
1140 1 approx. -1.4 Mhz ... +3.2Mhz */
1141 1 if ( oscFreq%divider_base > 2600 )
1142 1 {
1143 2 divider++;
1144 2 }
1145 1 if ( divider > CC_REG_REF_DIVIDE_D10 )
1146 1 {
1147 2 if ( oscFreq%divider_base > 3200 )
1148 2 {
1149 3 /* out of range */
1150 3 return (DRX_STS_ERROR);
1151 3 } else {
1152 3 /* still within upper tolerance range */
1153 3 divider--;
1154 3 }
1155 2 }
1156 1
1157 1 (extAttr->expectedSysClockFreq) = oscFreq*12/divider;
1158 1 /* rounding */
1159 1 if ( (2*((oscFreq*12)%divider)) > divider )
1160 1 {
1161 2 (extAttr->expectedSysClockFreq)++;
1162 2 }
1163 1
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 20
1164 1 if(oscFreq == 48000)
1165 1 {
1166 2 (extAttr->expectedSysClockFreq) = oscFreq;
1167 2 }
1168 1
1169 1 #ifndef COMPILE_FOR_QT
1170 1 /* 4-20 MHz pad */
1171 1 WR16( devAddr, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0x0000);
1172 1
1173 1 if ( oscFreq != 48000 )
1174 1 {
1175 2 /* active PLL, pump=1.2, outen = 0 */
1176 2 WR16( devAddr, CC_REG_PLL_MODE__A, ( CC_REG_PLL_MODE_BYPASS_PLL |
1177 2 CC_REG_PLL_MODE_PUMP_CUR_12 ) , 0);
1178 2 /* clock divider */
1179 2 WR16( devAddr, CC_REG_REF_DIVIDE__A, divider, 0);
1180 2 }
1181 1 else
1182 1 {
1183 2 /* 4-20 MHz pad, PLL bypassed */
1184 2 WR16( devAddr, CC_REG_PLL_MODE__A, 0x2 , 0);
1185 2 }
1186 1
1187 1 /* when power down , clock & PLL down, osc up */
1188 1 /* trigger CC to take over the new settings */
1189 1 WR16( devAddr, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY , 0);
1190 1 #endif
1191 1
1192 1 return (DRX_STS_OK);
1193 1
1194 1 #ifndef COMPILE_FOR_QT
1195 1 rw_error:
1196 1 return (DRX_STS_ERROR);
1197 1 #endif
1198 1
1199 1 }
1200
1201 /*============================================================================*/
1202
1203 /**
1204 * \fn DRXStatus_t InitFE( const pDRXDemodInstance_t demod )
1205 * \brief
1206 * \param demod pointer to demod data.
1207 * \return DRXStatus_t Return status.
1208 *\retval DRX_STS_OK Success.
1209 *\retval DRX_STS_ERROR Failure.
1210 */
1211 static DRXStatus_t
1212 InitFE( const pDRXDemodInstance_t demod )
1213 {
1214 1 pI2CDeviceAddr_t devAddr=NULL;
1215 1 pDRX3973DData_t extAttr=NULL;
1216 1
1217 1 #if (DRXD_TYPE_A)
1218 1
1219 1 static u8_t resetData1[] =
1220 1 { 0x00,0x00, /* FE_AD_REG_PD__A */
1221 1 0x01,0x00, /* FE_AD_REG_INVEXT__A */
1222 1 0x00,0x00 /* FE_AD_REG_CLKNEG__A */
1223 1 };
1224 1
1225 1 static u8_t resetData2[] =
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 21
1226 1 { 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
1227 1 0x10,0x00 /* FE_AG_REG_DCE_RUR_CNT__A */
1228 1 };
1229 1
1230 1 static u8_t resetData3[] =
1231 1 { 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
1232 1 0x00,0x00 /* FE_AG_REG_ACE_RUR_CNT__A */
1233 1 };
1234 1
1235 1 static u8_t resetData4[] =
1236 1 { 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
1237 1 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
1238 1 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
1239 1 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */
1240 1 0x00,0x00 /* FE_AG_REG_EGC_FLA_DEC__A */
1241 1 };
1242 1
1243 1 static u8_t resetData5[] =
1244 1 { 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
1245 1 0x00,0xFE /* FE_AG_REG_GC1_AGC_MIN__A */
1246 1 };
1247 1
1248 1 static u8_t resetData6[] =
1249 1 { 0x00,0x00, /* FE_AG_REG_IND_WIN__A */
1250 1 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */
1251 1 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */
1252 1 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */
1253 1 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */
1254 1 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
1255 1 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
1256 1 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
1257 1 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
1258 1 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */
1259 1 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
1260 1 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
1261 1 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
1262 1 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
1263 1 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
1264 1 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
1265 1 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */
1266 1 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
1267 1 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
1268 1 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
1269 1 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
1270 1 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */
1271 1 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
1272 1 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
1273 1 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */
1274 1 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */
1275 1 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
1276 1 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
1277 1 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
1278 1 };
1279 1
1280 1 static u8_t resetData7[] =
1281 1 { 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
1282 1 0x00,0x00 /* FE_AG_REG_BGC_CGC_WRI__A */
1283 1 };
1284 1
1285 1 static u8_t resetData8[] =
1286 1 { 0x05,0x00, /* FE_FD_REG_SCL__A */
1287 1 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 22
1288 1 0x05,0x00 /* FE_FD_REG_NR__A */
1289 1 };
1290 1
1291 1 static u8_t resetData9[] =
1292 1 { 0x16,0x00, /* FE_CF_REG_SCL__A */
1293 1 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */
1294 1 0x06,0x00, /* FE_CF_REG_NR__A */
1295 1 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */
1296 1 0x01,0x00 /* FE_CF_REG_MEAS_VAL__A */
1297 1 };
1298 1
1299 1 static u8_t resetData10[] =
1300 1 { 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */
1301 1 0x00,0x00 /* FE_CU_REG_FRM_CNT_STR__A */
1302 1 };
1303 1
1304 1
1305 1 devAddr = demod -> myI2CDevAddr;
1306 1 extAttr = (pDRX3973DData_t) demod -> myExtAttr;
1307 1
1308 1 WRBLOCK( devAddr, FE_AD_REG_PD__A , sizeof(resetData1), resetData1 );
1309 1 WRBLOCK( devAddr, FE_AG_REG_DCE_AUR_CNT__A , sizeof(resetData2), resetData2 );
1310 1 WRBLOCK( devAddr, FE_AG_REG_ACE_AUR_CNT__A , sizeof(resetData3), resetData3 );
1311 1 WRBLOCK( devAddr, FE_AG_REG_EGC_FLA_RGN__A , sizeof(resetData4), resetData4 );
1312 1 WRBLOCK( devAddr, FE_AG_REG_GC1_AGC_MAX__A , sizeof(resetData5), resetData5 );
1313 1 WRBLOCK( devAddr, FE_AG_REG_IND_WIN__A , sizeof(resetData6), resetData6 );
1314 1 WRBLOCK( devAddr, FE_AG_REG_BGC_FGC_WRI__A , sizeof(resetData7), resetData7 );
1315 1 WRBLOCK( devAddr, FE_FD_REG_SCL__A , sizeof(resetData8), resetData8 );
1316 1 WRBLOCK( devAddr, FE_CF_REG_SCL__A , sizeof(resetData9), resetData9 );
1317 1 WRBLOCK( devAddr, FE_CU_REG_FRM_CNT_RST__A , sizeof(resetData10), resetData10 );
1318 1
1319 1
1320 1 /* with or without PGA */
1321 1 if ( ( demod->myDemodFunct->typeId == DRX3973D_TYPE_ID ) ||
1322 1 ( demod->myDemodFunct->typeId == DRX3974D_TYPE_ID ) ||
1323 1 ( demod->myDemodFunct->typeId == DRX3977D_TYPE_ID ) )
1324 1 {
1325 2 /* with PGA */
1326 2 WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0004, 0x0000);
1327 2 } else {
1328 2 /* withou PGA */
1329 2 WR16( devAddr, FE_AG_REG_AG_PGA_MODE__A , 0x0001, 0x0000);
1330 2 }
1331 1 WR16( devAddr, FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );
1332 1 WR16( devAddr, FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );
1333 1 WR16( devAddr, FE_AG_REG_CDR_RUR_CNT__A, 0x0010, 0x0000 );
1334 1 WR16( devAddr, FE_AG_REG_FGM_WRI__A , 48, 0x0000 );
1335 1 /* Activate measurement, activate scale */
1336 1 WR16( devAddr, FE_FD_REG_MEAS_VAL__A , 0x0001, 0x0000 );
1337 1
1338 1 WR16( devAddr, FE_CU_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1339 1 WR16( devAddr, FE_CF_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1340 1 WR16( devAddr, FE_IF_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1341 1 WR16( devAddr, FE_FD_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1342 1 WR16( devAddr, FE_FS_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1343 1 WR16( devAddr, FE_AD_REG_COMM_EXEC__A , 0x0001, 0x0000);
1344 1 WR16( devAddr, FE_AG_REG_COMM_EXEC__A , 0x0001, 0x0000);
1345⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -