📄 drx3973d.lst
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801 1 if ( ( data == NULL ) ||
802 1 ( devAddr == NULL ) ||
803 1 ( (datasize%2)!=0 )
804 1 )
805 1 {
806 2 return (DRX_STS_INVALID_ARG);
807 2 }
808 1
809 1 /* Instruct HI to read n bytes */
810 1 hiCmd.cmd = HI_RA_RAM_SRV_CMD_EXECUTE;
811 1 hiCmd.param1 = (u16_t) (HI_TR_FUNC_ADDR & 0xFFFF);
812 1 hiCmd.param2 = (u16_t)(addr >> 16);
813 1 hiCmd.param3 = (u16_t)(addr & 0xFFFF);
814 1 hiCmd.param4 = (u16_t)((datasize/2) - 1);
815 1 hiCmd.param5 = HI_TR_READ;
816 1
817 1 CHK_ERROR( HI_Command( devAddr, &hiCmd, &dummy) );
818 1
819 1 for (i = 0; i < (datasize/2); i++)
820 1 {
821 2 u16_t word;
822 2
823 2 RR16 (devAddr, (HI_RA_RAM_USR_BEGIN__A + i), &word, 0);
824 2 data[2*i] = (u8_t) (word & 0xFF);
825 2 data[(2*i) + 1] = (u8_t) (word >> 8 );
826 2 }
827 1
828 1 return DRX_STS_OK;
829 1
830 1 rw_error:
831 1 return (DRX_STS_ERROR);
832 1 }
833
834 /*============================================================================*/
835
836 /**
837 * \fn DRXStatus_t AtomicReadReg32()
838 * \brief Atomic read of 32 bits words
839 */
840
841 static
842 DRXStatus_t AtomicReadReg32 (
843 pI2CDeviceAddr_t devAddr,
844 DRXaddr_t addr,
845 pu32_t data,
846 DRXflags_t flags)
847 {
848 1 u8_t buf[sizeof (*data)];
849 1 DRXStatus_t rc = DRX_STS_ERROR;
850 1 u32_t word = 0;
851 1
852 1 if (!data)
853 1 {
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 15
854 2 return DRX_STS_INVALID_ARG;
855 2 }
856 1
857 1 rc = AtomicReadBlock (devAddr, addr, sizeof (*data), buf, flags);
858 1
859 1 word = (u32_t)buf[3];
860 1 word <<= 8;
861 1 word |= (u32_t)buf[2];
862 1 word <<= 8;
863 1 word |= (u32_t)buf[1];
864 1 word <<= 8;
865 1 word |= (u32_t)buf[0];
866 1
867 1 *data = word;
868 1
869 1 return rc;
870 1 }
871
872 /*============================================================================*/
873
874 #if 0
/**
* \fn DRXStatus_t TunetI2CWriteRead()
* \brief I2C communication for tuner via micro
*/
DRXStatus_t TunerI2CWriteRead( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData)
{
pDRXDemodInstance_t demod;
DRXI2CData_t i2cData = { 1, wDevAddr, wCount, wData, rDevAddr, rCount, rData };
demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData);
return ( DRX_Ctrl( demod, DRX_CTRL_I2C_READWRITE, &i2cData ) );
}
#endif
895
896
897 /*=============================================================================
898 ===== Reset related funtions ================================================
899 ===========================================================================*/
900
901 /**
902 * \fn DRXStatus_t StopAllProcessors( const pI2CDeviceAddr_t devAddr )
903 * \brief Stop all processors except the HI.
904 * \param devAddr pointer to device address.
905 * \return DRXStatus_t Return status.
906 */
907 static DRXStatus_t
908 StopAllProcessors( const pI2CDeviceAddr_t devAddr )
909 {
910 1
911 1 /* Do not stop HI controller!
912 1 Otherwise there will be no communication with the device */
913 1 /* Do inverse broadcast, write to all blocks except the HI block
914 1 and CC block */
915 1 BCWR16( devAddr, HI_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP );
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 16
916 1
917 1 return (DRX_STS_OK);
918 1
919 1 rw_error:
920 1 return (DRX_STS_ERROR);
921 1 }
922
923 /*============================================================================*/
924
925 /**
926 * \fn DRXStatus_t EnableAndResetMB( const pI2CDeviceAddr_t devAddr )
927 * \brief Enable and reset monitor bus.
928 * \param devAddr pointer to device address.
929 * \return DRXStatus_t Return status.
930 */
931 static DRXStatus_t
932 EnableAndResetMB( const pI2CDeviceAddr_t devAddr )
933 {
934 1 #if (DRXD_TYPE_A)
935 1 /* disable? monitor bus observe @ EC_OC */
936 1 WR16( devAddr, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
937 1 #endif
938 1
939 1 /* Do inverse broadcast, followed by explicit write to HI */
940 1 BCWR16( devAddr, HI_COMM_MB__A, 0x0000 );
941 1 WR16( devAddr, HI_COMM_MB__A, 0x0000, 0x0000);
942 1
943 1 return (DRX_STS_OK);
944 1
945 1 rw_error:
946 1 return (DRX_STS_ERROR);
947 1 }
948
949 /*============================================================================*/
950
951 /**
952 * \fn DRXStatus_t ResetCE_FR( const pI2CDeviceAddr_t devAddr )
953 * \brief Reset CE FR.
954 * \param devAddr pointer to device address.
955 * \return DRXStatus_t Return status.
956 * \retval DRX_STS_OK Success.
957 * \retval DRX_STS_ERROR Failure.
958 *
959 * Due to bug in HW the default values of these registers have
960 * to be programmed by the host.
961 *
962 */
963 #if (DRXD_TYPE_A)
964
965 static DRXStatus_t
966 ResetCEFR( const pI2CDeviceAddr_t devAddr )
967 {
968 1
969 1 static u8_t resetData[] =
970 1 { 0x52,0x00, /* CE_REG_FR_TREAL00__A */
971 1 0x00,0x00, /* CE_REG_FR_TIMAG00__A */
972 1 0x52,0x00, /* CE_REG_FR_TREAL01__A */
973 1 0x00,0x00, /* CE_REG_FR_TIMAG01__A */
974 1 0x52,0x00, /* CE_REG_FR_TREAL02__A */
975 1 0x00,0x00, /* CE_REG_FR_TIMAG02__A */
976 1 0x52,0x00, /* CE_REG_FR_TREAL03__A */
977 1 0x00,0x00, /* CE_REG_FR_TIMAG03__A */
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 17
978 1 0x52,0x00, /* CE_REG_FR_TREAL04__A */
979 1 0x00,0x00, /* CE_REG_FR_TIMAG04__A */
980 1 0x52,0x00, /* CE_REG_FR_TREAL05__A */
981 1 0x00,0x00, /* CE_REG_FR_TIMAG05__A */
982 1 0x52,0x00, /* CE_REG_FR_TREAL06__A */
983 1 0x00,0x00, /* CE_REG_FR_TIMAG06__A */
984 1 0x52,0x00, /* CE_REG_FR_TREAL07__A */
985 1 0x00,0x00, /* CE_REG_FR_TIMAG07__A */
986 1 0x52,0x00, /* CE_REG_FR_TREAL08__A */
987 1 0x00,0x00, /* CE_REG_FR_TIMAG08__A */
988 1 0x52,0x00, /* CE_REG_FR_TREAL09__A */
989 1 0x00,0x00, /* CE_REG_FR_TIMAG09__A */
990 1 0x52,0x00, /* CE_REG_FR_TREAL10__A */
991 1 0x00,0x00, /* CE_REG_FR_TIMAG10__A */
992 1 0x52,0x00, /* CE_REG_FR_TREAL11__A */
993 1 0x00,0x00, /* CE_REG_FR_TIMAG11__A */
994 1
995 1 0x52,0x00, /* CE_REG_FR_MID_TAP__A */
996 1
997 1 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */
998 1 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */
999 1 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */
1000 1 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */
1001 1 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */
1002 1 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */
1003 1 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */
1004 1 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */
1005 1 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */
1006 1 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */
1007 1 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */
1008 1 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */
1009 1 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */
1010 1
1011 1 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */
1012 1 0x90,0x01, /* CE_REG_FR_RIO_G01__A */
1013 1 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */
1014 1 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */
1015 1 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */
1016 1 0x85,0x00, /* CE_REG_FR_RIO_G05__A */
1017 1 0x72,0x00, /* CE_REG_FR_RIO_G06__A */
1018 1 0x64,0x00, /* CE_REG_FR_RIO_G07__A */
1019 1 0x59,0x00, /* CE_REG_FR_RIO_G08__A */
1020 1 0x50,0x00, /* CE_REG_FR_RIO_G09__A */
1021 1 0x49,0x00, /* CE_REG_FR_RIO_G10__A */
1022 1
1023 1 0x10,0x00, /* CE_REG_FR_MODE__A */
1024 1 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */
1025 1 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */
1026 1 0x00,0x02, /* CE_REG_FR_BYPASS__A */
1027 1 0x0D,0x00, /* CE_REG_FR_PM_SET__A */
1028 1 0x07,0x00, /* CE_REG_FR_ERR_SH__A */
1029 1 0x04,0x00, /* CE_REG_FR_MAN_SH__A */
1030 1 0x06,0x00 /* CE_REG_FR_TAP_SH__A */
1031 1 };
1032 1
1033 1 WRBLOCK( devAddr, CE_REG_FR_TREAL00__A, sizeof(resetData), resetData );
1034 1
1035 1
1036 1 return (DRX_STS_OK);
1037 1
1038 1 rw_error:
1039 1 return (DRX_STS_ERROR);
C51 COMPILER V8.02 DRX3973D 02/11/2009 09:42:41 PAGE 18
1040 1 }
1041
1042 #endif /* DRXD_TYPE_A */
1043
1044 /*============================================================================*/
1045
1046 /**
1047 * \fn DRXStatus_t SetDeviceTypeId( const pDRXDemodInstance_t demod )
1048 * \brief Determine and set typeId of device.
1049 * \param demod pointer to demod instance.
1050 * \return DRXStatus_t Return status.
1051 * \retval DRX_STS_OK Success.
1052 * \retval DRX_STS_ERROR Failure.
1053 *
1054 */
1055 static DRXStatus_t
1056 SetDeviceTypeId( const pDRXDemodInstance_t demod )
1057 {
1058 1 pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr;
1059 1 u16_t deviceId = 0 ;
1060 1 DRXStatus_t status = DRX_STS_OK;
1061 1
1062 1 RR16( devAddr, CC_REG_JTAGID_L__A , &deviceId, 0x0000);
1063 1
1064 1 if ( deviceId == 0 )
1065 1 {
1066 2 /* DRXD_TYPE_A , DRX3975D only type available */
1067 2 demod->myDemodFunct->typeId = DRX3975D_TYPE_ID;
1068 2 } else {
1069 2 /* DRXD_TYPE_B */
1070 2 deviceId = deviceId >> 12;
1071 2 switch ( deviceId )
1072 2 {
1073 3 case 3 :
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