ext_ring_dete.vhd

响铃和内存管理功能的VHDL语言

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--
-- Title       : EXT_RING_DETE
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : EXT_RING_DETE.vhd
-- Generated   : Tue Nov  4 13:37:53 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {da_control} architecture {arch}}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ext_ring_dete is
	port (
	CLK : in std_logic;
	PASSC_TMP : in std_logic;
	CLR : in std_logic;
	RING_D : in std_logic;
	EXT_STA:  out std_logic;
	EXT_RING_DETECTED : out std_logic
	);
end ext_ring_dete;

architecture a of ext_ring_dete	is

component debouncing
   port (DIN ,CLK : IN STD_LOGIC;
   		 DOUT : OUT STD_LOGIC) ;
end component ;

signal RING_TMP,DETE_RING,EXT_RING_DETECTED_TMP,T1,UP,DN: std_logic;
signal SEG: std_logic_vector(1 downto 0);
signal EXT_STA_TMP: std_logic;
begin
EXT_RING_DETECTED <= EXT_RING_DETECTED_TMP;	
RING_TMP<= not RING_D;
EXT_STA <= RING_D;
--DETECTED_RING: debouncing
--port map
--	(
--		DIN => RING_TMP,
--		CLK => CLK,
--		DOUT => DETE_RING
--	);
DETE_RING <=	 RING_TMP;

	process (CLR,DETE_RING,SEG,CLK,PASSC_TMP)
	begin
		if CLR='1' then
			SEG<="00";
			T1<='0';
			EXT_RING_DETECTED_TMP <='1';
			DN <='0';
			UP <= '0';
			EXT_STA_TMP <= '0';
		elsif rising_edge(CLK) then
			T1<=DETE_RING;
		    if DETE_RING='0' and T1= '1'then
				DN<='1';
			else
				DN<='0';
			end if;
		    if DETE_RING='1' and T1= '0'then
				UP<='1';
			else
				UP<='0';
			end if;
			case SEG is
			when "00" =>
					if DN = '1' then
						SEG <= "01";
						EXT_RING_DETECTED_TMP <= '1';
						EXT_STA_TMP <= '1';
					else
						SEG <= SEG;
						EXT_RING_DETECTED_TMP<=EXT_RING_DETECTED_TMP;
					end if;
				when "01" =>
					if UP ='1' then
						SEG <= "10";
						EXT_RING_DETECTED_TMP <= '0';
					else
						SEG <= SEG;
						EXT_RING_DETECTED_TMP<=EXT_RING_DETECTED_TMP;
					end if;
                when "10"=> 
                    if DN ='1' then
                        SEG <="11";
                        EXT_RING_DETECTED_TMP <= '1';
					else
						SEG <= SEG;
						EXT_RING_DETECTED_TMP<=EXT_RING_DETECTED_TMP;
                    end if;
				when "11" =>
					if PASSC_TMP='1' then
						SEG <= "00";
						EXT_STA_TMP<= '0';
					else
						SEG <= SEG;
						EXT_RING_DETECTED_TMP<=EXT_RING_DETECTED_TMP;
					end if;
				when others => SEG<= SEG;
			end case;
		end if;					
	end process;
end a;