dsp_port_test_ss7.vhd

响铃和内存管理功能的VHDL语言

-- VHDL Test Bench Created from source file dsp_port.vhd -- 15:19:22 07/14/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all; 
ENTITY dsp_port_dsp_port_test_ss7_vhd_tb IS
END dsp_port_dsp_port_test_ss7_vhd_tb;

ARCHITECTURE behavior OF dsp_port_dsp_port_test_ss7_vhd_tb IS 

  COMPONENT dsp_port
  PORT(
    A : IN std_logic_vector(22 downto 0);
    XF : IN std_logic;
    IOSTRB : IN std_logic;
    MSTRB : IN std_logic;
    DSP_RW : IN std_logic;
    DSPIS : IN std_logic;
    DS : IN std_logic;
    PS : IN std_logic;
    DSP_CLKOUT_IN : IN std_logic;
    FLASH_WE_EN : IN std_logic;
    AD1_OUT : IN std_logic;
    AD2_OUT : IN std_logic;
    AD3_OUT : IN std_logic;
    AD4_OUT : IN std_logic;
    AD5_OUT : IN std_logic;
    M1_SHK : IN std_logic;
    M2_SHK : IN std_logic;
    M3_SHK : IN std_logic;
    M4_SHK : IN std_logic;
    RING_D : IN std_logic;
    PCM_AT : IN std_logic;
    PCM_BT : IN std_logic;
    PCM_CT : IN std_logic;
    PCM_DT : IN std_logic;
    PCM_ET : IN std_logic;
    TR_PCMR : IN std_logic;
    ss7_rxd : IN std_logic;
    TR_BR_IN : IN std_logic;
    KEY : IN std_logic_vector(5 downto 0);
    SYS_CLK_IN : IN std_logic;
    RST_IN : IN std_logic;
    rxd : IN std_logic;    
    D_IN : INOUT std_logic_vector(15 downto 0);
    LCD_D : INOUT std_logic_vector(7 downto 0);
    EXT_RAM_D : INOUT std_logic_vector(7 downto 0);      
    SRAM_CE : OUT std_logic;
    SRAM_OE : OUT std_logic;
    SRAM_WE : OUT std_logic;
    FLASH_CE : OUT std_logic;
    FLASH_OE : OUT std_logic;
    FLASH_WE : OUT std_logic;
    IC2_TR : OUT std_logic;
    LCD_RD : OUT std_logic;
    LCD_WR : OUT std_logic;
    LCD_CD : OUT std_logic;
    LCD_CE : OUT std_logic;
    U38_OE1 : OUT std_logic;
    U38_OE2 : OUT std_logic;
    U38_TR1 : OUT std_logic;
    U38_TR2 : OUT std_logic;
    LCD_RST : OUT std_logic;
    CLK_AD : OUT std_logic;
    AD1_CS : OUT std_logic;
    AD2_CS : OUT std_logic;
    AD3_CS : OUT std_logic;
    AD4_CS : OUT std_logic;
    AD5_CS : OUT std_logic;
    DA_DIN : OUT std_logic_vector(1 downto 0);
    DA_CS : OUT std_logic_vector(1 downto 0);
    DA_CLK : OUT std_logic_vector(1 downto 0);
    USER_RC : OUT std_logic_vector(3 downto 0);
    PASSC : OUT std_logic;
    PCM_AR : OUT std_logic;
    PCM_BR : OUT std_logic;
    PCM_CR : OUT std_logic;
    PCM_DR : OUT std_logic;
    PCM_ER : OUT std_logic;
    FS_AR : OUT std_logic;
    FS_BR : OUT std_logic;
    FS_CR : OUT std_logic;
    FS_DR : OUT std_logic;
    FS_ER : OUT std_logic;
    FS_AT : OUT std_logic;
    FS_BT : OUT std_logic;
    FS_CT : OUT std_logic;
    FS_DT : OUT std_logic;
    FS_ET : OUT std_logic;
    PCM_BS : OUT std_logic;
    TR_PCMX : OUT std_logic;
    ss7_txd : OUT std_logic;
    TR_BX : OUT std_logic;
    EXT_RAM_A : OUT std_logic_vector(14 downto 0);
    EXT_RAM_OE : OUT std_logic;
    EXT_RAM_CE : OUT std_logic;
    EXT_RAM_WR : OUT std_logic;
    connect_pc : OUT std_logic;
    txd : OUT std_logic;
    uart_int : OUT std_logic;
    dsp_clk_divout : OUT std_logic
    );
  END COMPONENT;

  SIGNAL D_IN :  std_logic_vector(15 downto 0);
  SIGNAL A :  std_logic_vector(22 downto 0);
  SIGNAL XF :  std_logic;
  SIGNAL IOSTRB :  std_logic;
  SIGNAL MSTRB :  std_logic;
  SIGNAL DSP_RW :  std_logic;
  SIGNAL DSPIS :  std_logic;
  SIGNAL DS :  std_logic;
  SIGNAL PS :  std_logic;
  SIGNAL DSP_CLKOUT_IN :  std_logic;
  SIGNAL SRAM_CE :  std_logic;
  SIGNAL SRAM_OE :  std_logic;
  SIGNAL SRAM_WE :  std_logic;
  SIGNAL FLASH_CE :  std_logic;
  SIGNAL FLASH_OE :  std_logic;
  SIGNAL FLASH_WE :  std_logic;
  SIGNAL FLASH_WE_EN :  std_logic;
  SIGNAL IC2_TR :  std_logic;
  SIGNAL LCD_D :  std_logic_vector(7 downto 0);
  SIGNAL LCD_RD :  std_logic;
  SIGNAL LCD_WR :  std_logic;
  SIGNAL LCD_CD :  std_logic;
  SIGNAL LCD_CE :  std_logic;
  SIGNAL U38_OE1 :  std_logic;
  SIGNAL U38_OE2 :  std_logic;
  SIGNAL U38_TR1 :  std_logic;
  SIGNAL U38_TR2 :  std_logic;
  SIGNAL LCD_RST :  std_logic;
  SIGNAL CLK_AD :  std_logic;
  SIGNAL AD1_OUT :  std_logic;
  SIGNAL AD1_CS :  std_logic;
  SIGNAL AD2_OUT :  std_logic;
  SIGNAL AD2_CS :  std_logic;
  SIGNAL AD3_OUT :  std_logic;
  SIGNAL AD3_CS :  std_logic;
  SIGNAL AD4_OUT :  std_logic;
  SIGNAL AD4_CS :  std_logic;
  SIGNAL AD5_OUT :  std_logic;
  SIGNAL AD5_CS :  std_logic;
  SIGNAL DA_DIN :  std_logic_vector(1 downto 0);
  SIGNAL DA_CS :  std_logic_vector(1 downto 0);
  SIGNAL DA_CLK :  std_logic_vector(1 downto 0);
  SIGNAL M1_SHK :  std_logic;
  SIGNAL M2_SHK :  std_logic;
  SIGNAL M3_SHK :  std_logic;
  SIGNAL M4_SHK :  std_logic;
  SIGNAL USER_RC :  std_logic_vector(3 downto 0);
  SIGNAL RING_D :  std_logic;
  SIGNAL PASSC :  std_logic;
  SIGNAL PCM_AT :  std_logic;
  SIGNAL PCM_BT :  std_logic;
  SIGNAL PCM_CT :  std_logic;
  SIGNAL PCM_DT :  std_logic;
  SIGNAL PCM_ET :  std_logic;
  SIGNAL PCM_AR :  std_logic;
  SIGNAL PCM_BR :  std_logic;
  SIGNAL PCM_CR :  std_logic;
  SIGNAL PCM_DR :  std_logic;
  SIGNAL PCM_ER :  std_logic;
  SIGNAL FS_AR :  std_logic;
  SIGNAL FS_BR :  std_logic;
  SIGNAL FS_CR :  std_logic;
  SIGNAL FS_DR :  std_logic;
  SIGNAL FS_ER :  std_logic;
  SIGNAL FS_AT :  std_logic;
  SIGNAL FS_BT :  std_logic;
  SIGNAL FS_CT :  std_logic;
  SIGNAL FS_DT :  std_logic;
  SIGNAL FS_ET :  std_logic;
  SIGNAL PCM_BS :  std_logic;
  SIGNAL TR_PCMX :  std_logic;
  SIGNAL ss7_txd :  std_logic;
  SIGNAL TR_BX :  std_logic;
  SIGNAL TR_PCMR :  std_logic;
  SIGNAL ss7_rxd :  std_logic;
  SIGNAL TR_BR_IN :  std_logic;
  SIGNAL EXT_RAM_D :  std_logic_vector(7 downto 0);
  SIGNAL EXT_RAM_A :  std_logic_vector(14 downto 0);
  SIGNAL EXT_RAM_OE :  std_logic;
  SIGNAL EXT_RAM_CE :  std_logic;
  SIGNAL EXT_RAM_WR :  std_logic;
  SIGNAL KEY :  std_logic_vector(5 downto 0);
  SIGNAL SYS_CLK_IN :  std_logic;
  SIGNAL RST_IN :  std_logic;
  SIGNAL connect_pc :  std_logic;
  SIGNAL txd :  std_logic;
  SIGNAL rxd :  std_logic;
  SIGNAL uart_int :  std_logic;
  SIGNAL dsp_clk_divout :  std_logic;
signal framelength: std_logic_vector(7 downto 0):="11111111";
BEGIN

  uut: dsp_port PORT MAP(
    D_IN => D_IN,
    A => A,
    XF => XF,
    IOSTRB => IOSTRB,
    MSTRB => MSTRB,
    DSP_RW => DSP_RW,
    DSPIS => DSPIS,
    DS => DS,
    PS => PS,
    DSP_CLKOUT_IN => DSP_CLKOUT_IN,
    SRAM_CE => SRAM_CE,
    SRAM_OE => SRAM_OE,
    SRAM_WE => SRAM_WE,
    FLASH_CE => FLASH_CE,
    FLASH_OE => FLASH_OE,
    FLASH_WE => FLASH_WE,
    FLASH_WE_EN => FLASH_WE_EN,
    IC2_TR => IC2_TR,
    LCD_D => LCD_D,
    LCD_RD => LCD_RD,
    LCD_WR => LCD_WR,
    LCD_CD => LCD_CD,
    LCD_CE => LCD_CE,
    U38_OE1 => U38_OE1,
    U38_OE2 => U38_OE2,
    U38_TR1 => U38_TR1,
    U38_TR2 => U38_TR2,
    LCD_RST => LCD_RST,
    CLK_AD => CLK_AD,
    AD1_OUT => AD1_OUT,
    AD1_CS => AD1_CS,
    AD2_OUT => AD2_OUT,
    AD2_CS => AD2_CS,
    AD3_OUT => AD3_OUT,
    AD3_CS => AD3_CS,
    AD4_OUT => AD4_OUT,
    AD4_CS => AD4_CS,
    AD5_OUT => AD5_OUT,
    AD5_CS => AD5_CS,
    DA_DIN => DA_DIN,
    DA_CS => DA_CS,
    DA_CLK => DA_CLK,
    M1_SHK => M1_SHK,
    M2_SHK => M2_SHK,
    M3_SHK => M3_SHK,
    M4_SHK => M4_SHK,
    USER_RC => USER_RC,
    RING_D => RING_D,
    PASSC => PASSC,
    PCM_AT => PCM_AT,
    PCM_BT => PCM_BT,
    PCM_CT => PCM_CT,
    PCM_DT => PCM_DT,
    PCM_ET => PCM_ET,
    PCM_AR => PCM_AR,
    PCM_BR => PCM_BR,
    PCM_CR => PCM_CR,
    PCM_DR => PCM_DR,
    PCM_ER => PCM_ER,
    FS_AR => FS_AR,
    FS_BR => FS_BR,
    FS_CR => FS_CR,
    FS_DR => FS_DR,
    FS_ER => FS_ER,
    FS_AT => FS_AT,
    FS_BT => FS_BT,
    FS_CT => FS_CT,
    FS_DT => FS_DT,
    FS_ET => FS_ET,
    PCM_BS => PCM_BS,
    TR_PCMX => TR_PCMX,
    ss7_txd => ss7_txd,
    TR_BX => TR_BX,
    TR_PCMR => TR_PCMR,
    ss7_rxd => ss7_rxd,
    TR_BR_IN => TR_BR_IN,
    EXT_RAM_D => EXT_RAM_D,
    EXT_RAM_A => EXT_RAM_A,
    EXT_RAM_OE => EXT_RAM_OE,
    EXT_RAM_CE => EXT_RAM_CE,
    EXT_RAM_WR => EXT_RAM_WR,
    KEY => KEY,
    SYS_CLK_IN => SYS_CLK_IN,
    RST_IN => RST_IN,
    connect_pc => connect_pc,
    txd => txd,
    rxd => rxd,
    uart_int => uart_int,
    dsp_clk_divout => dsp_clk_divout
  );



   DSP_CLK_GEN: PROCESS
   BEGIN               -- 80M
      DSP_CLKOUT_IN <= '0';
    WAIT FOR 5.9952380952380952380952380952381 ns;
      DSP_CLKOUT_IN <= '1';
    wait for 5.9952380952380952380952380952381 ns;
   END PROCESS DSP_CLK_GEN;

  sys_clk_gen:process
  begin              --16.384M
    SYS_CLK_IN <='0';
    wait for 30.517578125 ns;
    SYS_CLK_IN <='1';
    wait for 30.517578125 ns;
  end process sys_clk_gen;

  CLR_gen:process
  begin
    RST_IN <='0';
    wait for 12 ns;
    RST_IN <='1';
    wait;
  end process clr_gen;

process
  variable counter     : std_logic_vector(7 downto 0) := "00000000";  -- Internal counter

   BEGIN
			D_IN <=(others=>'Z');
			A <= (others=>'0');
			XF <= '1';
			IOSTRB <='1';
			MSTRB <='1';
			DSP_RW <='1';
			DSPIS <='1';
			DS <='1';
			PS <='1';
			DSPIS <= '1';
			FLASH_WE_EN <='1';
			key <= (others => '1');
   wait for 100 ns;
--   wait until _tx_busy ='0';
   wait until DSP_CLKOUT_IN = '0';
   counter := "10100000";

   for i in 0 to 3 loop

      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      D_IN <= "0000000001111110";
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='0';
      wait until DSP_CLKOUT_IN ='1';
      wait until DSP_CLKOUT_IN ='0';
      a<="000"& X"00013";--ss7tx_fifo_cs <='0';
      IOSTRB <='0';