da_control.vhd

VHDL语言的ADDA（模数数模置换）控制

---------------------------------------------------------------------------------------------------
--
-- Title       : da_control
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
---------------------------------------------------------------------------------------------------
--
-- File        : da_control.vhd
-- Generated   : Tue Nov  4 13:37:53 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {da_control} architecture {arch}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;  

Library work;
use work.all;

entity da_control is
port(  
    DATA : in std_logic_vector( 15 downto 0);
    DA_CLK,FIFO_WRCLK : in std_logic;--256K    
    WR : in std_logic;    --ACTIVE '0'
    CLR : in std_logic;
    DA_FF_CS : in std_logic_vector( 3 downto 0);
    DA_FF_FULL : out std_logic_vector ( 3 downto 0);
    DA_DATA : out std_logic_vector( 1 downto 0);
    DA_CLK_OUT : out std_logic_vector( 1 downto 0);
--  FFA_DOUT: out  std_logic_vector( 15 downto 0);    --test
    DA_LD_OUT : out std_logic_vector( 1 downto 0)
);
end da_control;

--}} End of automatically maintained section

architecture arch of da_control is


component serial_da
   port(  CLK2DA : in STD_LOGIC;
      NCS : in STD_LOGIC;
      CLO : out STD_LOGIC;
      LD : out STD_LOGIC;
      SO : out STD_LOGIC; 
      DIN_A  :in STD_LOGIC_VECTOR(11 downto 0);
      DIN_B  : in STD_LOGIC_VECTOR(11 downto 0));
end component ;

component fifo12x1024b   -- delay one clock's cycle
  port(
    WR_CS : in std_logic;
    RD_CS : in std_logic;
    CLR : in std_logic;
    CLK : in std_logic;
    RD : in std_logic;
    WR : in std_logic;  --ACTIVE '1'
    DATA : in std_logic_vector (11 downto 0);
    EMPTY : out std_logic;
    FULL : out std_logic;
    Q : out std_logic_vector (11 downto 0)
  );
end component;

--end add
  signal GND: STD_LOGIC ;  
  signal INV_WR,RD_TP : std_logic;
  signal DATA_TEMP : std_logic_vector( 11 downto 0);
  signal FFA_Q,FFB_Q,FFC_Q,FFD_Q : std_logic_vector ( 11 downto 0);
  signal FF_RD : std_logic_vector( 3 downto 0);
  signal FF_EP,FF_FU : std_logic_vector( 3 downto 0);
  signal DA_CS,DA_LD, DA_CLK_OUT_TMP: std_logic_vector( 1 downto 0);		 
  signal FF_CLOCK: std_logic;
begin  
  INV_WR <= not WR;
  GND <= '0';
--  RD_TP <= WR AND (NOT DA_FF_CS(1));
--  FFA_DOUT <= ffa_q & "1111";

process(CLR,FIFO_WRCLK)
begin
  if CLR ='1' then
    FF_CLOCK<='0' ;
  elsif rising_edge(FIFO_WRCLK)then
    FF_CLOCK <= not FF_CLOCK;
  end if;
end process;


INSERT_COMP: block         

begin 

  UUT1 : fifo12x1024b
  port map (
     WR_CS => DA_FF_CS(0),
    RD_CS => GND,
    CLR => CLR,
    CLK => FF_CLOCK,
    RD => FF_RD(0),   --ACTIVE '1'
    WR => INV_WR,     --ACTIVE '1'
    DATA => DATA_TEMP,
    EMPTY => FF_EP(0),
    FULL => FF_FU(0),
    Q => FFA_Q
    );
  UUT2 : fifo12x1024b
  port map (
     WR_CS => DA_FF_CS(1),--GND,  --1
    RD_CS => GND,
    CLR => CLR,
    CLK => FF_CLOCK,
    RD => FF_RD(1),
    WR => INV_WR,-- FLAG,
    DATA => DATA_TEMP,--ff_data_in,
    EMPTY => FF_EP(1),
    FULL => FF_FU(1),
    Q => FFB_Q
    );
  UUT3 : fifo12x1024b
  port map (
     WR_CS => DA_FF_CS(2),
    RD_CS => GND,
    CLR => CLR,
    CLK => FF_CLOCK,
    RD => FF_RD(2),
    WR => INV_WR,
    DATA => DATA_TEMP,
    EMPTY => FF_EP(2),
    FULL => FF_FU(2),
    Q => FFC_Q
    );
  UUT4 : fifo12x1024b    
  port map (
     WR_CS => DA_FF_CS(3),
    RD_CS => GND,
    CLR => CLR,
    CLK => FF_CLOCK,
    RD => FF_RD(3),
    WR => INV_WR,
    DATA => DATA_TEMP,
    EMPTY => FF_EP(3),
    FULL => FF_FU(3),
    Q => FFD_Q
    );

DA1: serial_da
     port map (
        CLK2DA => DA_CLK, 
        NCS => DA_CS(0),
        CLO => DA_CLK_OUT_TMP(0),
        LD => DA_LD(0),
        SO => DA_DATA(0),
        DIN_A => FFA_Q, --ff_data_in,
        DIN_B => FFB_Q  --ff_data_in
        );
  DA2: serial_da
     port map (
        CLK2DA => DA_CLK, 
        NCS => DA_CS(1),
        CLO => DA_CLK_OUT_TMP(1),
        LD => DA_LD(1),
        SO => DA_DATA(1),
        DIN_A => FFC_Q,
        DIN_B => FFD_Q
        );  
end block INSERT_COMP;
CONNECTION : block      
begin
--process(FF_CLOCK,clr)
--begin
--if clr ='1' then
--  DA_CS(0) <= '1';
--  DA_CS(1) <= '1';
--  FF_RD(0) <= '0';
--  FF_RD(1) <= '0';
--  FF_RD(2) <= '0';
--  FF_RD(3) <= '0';
--  DA_LD_OUT <=(others=> '0');
-- DA_FF_FULL <= (others=>'0');
--  DATA_TEMP <= (others=>'0');
--  DA_CLK_OUT(0)<= '0';
--  DA_CLK_OUT(1)<= '0';
--elsif rising_edge(FF_CLOCK) then
  DA_LD_OUT <= DA_LD;
  DA_CS(0) <= (FF_EP(0) and FF_EP(1)) ;
  DA_CS(1) <= (FF_EP(2) and FF_EP(3)) ;
  FF_RD(0) <= ((not FF_EP(0)) and DA_LD(0)) ;
  FF_RD(1) <= ((not FF_EP(1)) and DA_LD(0)) ;
  FF_RD(2) <= ((not FF_EP(2)) and DA_LD(1)) ;
  FF_RD(3) <= ((not FF_EP(3)) and DA_LD(1)) ;
  DA_FF_FULL <= FF_FU;
  DATA_TEMP <= DATA(15 downto 4);
  DA_CLK_OUT(0)<= not  DA_CLK_OUT_TMP(0);
  DA_CLK_OUT(1)<= not  DA_CLK_OUT_TMP(1);
--end if;
--end process;
end block CONNECTION;
end arch;