afifo_32x8.vhd

VHDL语言的ADDA（模数数模置换）控制

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-- You must compile the wrapper file afifo_32x8.vhd when simulating
-- the core, afifo_32x8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY afifo_32x8 IS
  port (
  din: IN std_logic_VECTOR(7 downto 0);
  wr_en: IN std_logic;
  wr_clk: IN std_logic;
  rd_en: IN std_logic;
  rd_clk: IN std_logic;
  ainit: IN std_logic;
  dout: OUT std_logic_VECTOR(7 downto 0);
  full: OUT std_logic;
  empty: OUT std_logic;
  almost_full: OUT std_logic;
  almost_empty: OUT std_logic);
END afifo_32x8;

ARCHITECTURE afifo_32x8_a OF afifo_32x8 IS

component wrapped_afifo_32x8
  port (
  din: IN std_logic_VECTOR(7 downto 0);
  wr_en: IN std_logic;
  wr_clk: IN std_logic;
  rd_en: IN std_logic;
  rd_clk: IN std_logic;
  ainit: IN std_logic;
  dout: OUT std_logic_VECTOR(7 downto 0);
  full: OUT std_logic;
  empty: OUT std_logic;
  almost_full: OUT std_logic;
  almost_empty: OUT std_logic);
end component;

-- Configuration specification 
  for all : wrapped_afifo_32x8 use entity XilinxCoreLib.async_fifo_v5_1(behavioral)
    generic map(
      c_use_blockmem => 1,
      c_rd_count_width => 2,
      c_has_wr_ack => 0,
      c_has_almost_full => 1,
      c_has_wr_err => 0,
      c_wr_err_low => 0,
      c_wr_ack_low => 0,
      c_data_width => 8,
      c_enable_rlocs => 0,
      c_rd_err_low => 0,
      c_wr_count_width => 2,
      c_rd_ack_low => 0,
      c_has_rd_count => 0,
      c_has_almost_empty => 1,
      c_has_rd_ack => 0,
      c_has_wr_count => 0,
      c_fifo_depth => 31,
      c_has_rd_err => 0);
BEGIN

U0 : wrapped_afifo_32x8
    port map (
      din => din,
      wr_en => wr_en,
      wr_clk => wr_clk,
      rd_en => rd_en,
      rd_clk => rd_clk,
      ainit => ainit,
      dout => dout,
      full => full,
      empty => empty,
      almost_full => almost_full,
      almost_empty => almost_empty);
END afifo_32x8_a;

-- synopsys translate_on