ad_control.vhd

来自「VHDL语言的ADDA（模数数模置换）控制」· VHDL 代码 · 共 420 行

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--
-- Title       : ad_control
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : ad_control.vhd
-- Generated   : Mon Nov 10 09:49:35 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--         
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {ad_control} architecture {a}}

  library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity ad_control is
  port(  CLK_AD : in std_logic; --256K
       AD_CLK : out std_logic;--128K
       RESET : in std_logic;
--AD1
         AD1_DATA_OUT : in std_logic;
         AD1_CS_IN : in std_logic;
      AD1_CS_OUT : out std_logic;
       AD1_DATA : out std_logic_vector(7 downto 0);

--AD2
         AD2_DATA_OUT : in std_logic;
         AD2_CS_IN : in std_logic;
      AD2_CS_OUT : out std_logic;
       AD2_DATA : out std_logic_vector(7 downto 0);
--AD3   
         AD3_DATA_OUT : in std_logic;
         AD3_CS_IN : in std_logic;
      AD3_CS_OUT : out std_logic;
       AD3_DATA : out std_logic_vector(7 downto 0);
--AD4
       AD4_DATA_OUT : in std_logic;
         AD4_CS_IN : in std_logic;
      AD4_CS_OUT : out std_logic;     
       AD4_DATA : out std_logic_vector(7 downto 0);
--AD5
         AD5_DATA_OUT : in std_logic;
         AD5_CS_IN : in std_logic;
      AD5_CS_OUT : out std_logic;
       AD5_DATA : out std_logic_vector(7 downto 0);
--       AD_FLAG_CLR : in std_logic_vector(4 downto 0);
       AD_FIFO_RDCLOCK : in std_logic;
       AD_FIFO_RD : in std_logic;  --ACTIVE '1'
       AD_FIFO_RDCS : in std_logic_vector(4 downto 0);
       AD_FLAG : out std_logic_vector(4 downto 0));
  
end ad_control;   

architecture a of ad_control is

component serial_ad
   PORT( CLKADI: IN STD_LOGIC;--AD's clock signal,128K
    CLR  : IN STD_LOGIC;--clr signal ,active '1'
    DAI  : IN STD_LOGIC;--AD output 
    NCS  : in STD_LOGIC;
    CS_OUT : out std_logic;
    FLGO : OUT STD_LOGIC;--AD output Data's FS signal
    DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--AD data output 7bit
end component ;

component fifo8x1024
  port (
    WR_CS : in std_logic;
    RD_CS : in std_logic;
    CLR : in std_logic;
    CLK : in std_logic;
    RD : in std_logic;  --ACTIVE '1'
    WR : in std_logic;   --ACTIVE '1'
    DATA : in std_logic_vector (7 downto 0);
    EMPTY : out std_logic;
    FULL : out std_logic;
	 AE,AF : out std_logic;
    Q : out std_logic_vector (7 downto 0)
    );
end component ;

signal AD_CLK_2,FF_CLOCK : std_logic;--  ,CLK_AD_INV
signal ZERO: STD_LOGIC ;
signal adcs1,adcs2,adcs3,adcs4,adcs5: std_logic;
begin 
--  CLK_AD_INV <= not CLK_AD;
  AD_CLK <= AD_CLK_2;
  ZERO <= '0';
  ad1_cs_out<=adcs1;
  ad2_cs_out<=adcs2;
  ad3_cs_out<=adcs3;
  ad4_cs_out<=adcs4;
  ad5_cs_out<=adcs5;

process(RESET,AD_FIFO_RDCLOCK)
begin
  if RESET ='1' then
    FF_CLOCK<='0' ;
  elsif rising_edge(AD_FIFO_RDCLOCK)then
    FF_CLOCK <= not FF_CLOCK;
  end if;
end process;


AD_CLOCK: block 
begin
  process(CLK_AD,RESET)
  begin
    if RESET ='1' then
      AD_CLK_2 <='0';
    elsif rising_edge(CLK_AD)then
      AD_CLK_2 <= not AD_CLK_2;
    end if;
  end process;
end block AD_CLOCK;

AD1_CONTROL:block
  signal AD1_DATA_TEMP,AD1_D_T: std_logic_vector( 7 downto 0);
  signal AD1_FS: std_logic;
  signal AD1_FIFO_RD : std_logic;
  signal WRFULL,WREMPTY : std_logic;
  signal AD_FLAG_TMP: std_logic;
  signal ae,af: std_logic;

--  signal test_fifo_q : std_logic_vector( 7 downto 0);
  begin
  AD1_FIFO_RD <= AD_FIFO_RD and (not AD_FIFO_RDCS(0));
  AD1_COMPONENT: serial_ad
     port map (
            CLKADI => AD_CLK_2,
            CLR => RESET ,
            DAI => AD1_DATA_OUT ,
            NCS => AD1_CS_IN ,
            CS_OUT => adcs1,
            FLGO => AD1_FS ,
            DOUT => AD1_DATA_TEMP
          ); 
  AD1_FIFO_COMPONENT:fifo8x1024
    port map (
      WR_CS => adcs1,
      RD_CS =>AD_FIFO_RDCS(0),
      CLR => RESET,
      CLK => FF_CLOCK,
      RD=> AD1_FIFO_RD,
      WR => AD1_FS, --ACTIVE '1'
      DATA => AD1_DATA_TEMP,
      EMPTY => WREMPTY,
      FULL => WRFULL,
		af => af,
		ae => ae,
      Q => AD1_D_T
    );
-- test fifo reader
--test_fifo:process(CLK_AD,RESET)
--begin
--  if reset = '1' then
--     test_fifo_q <= (others=> '0');
--  elsif rising_edge(CLK_AD) then
--    if test_fifo_q ="11111111" then
--        test_fifo_q <= (others=> '0');
--    else
--      if WRFULL = '0' then
--        test_fifo_q <= test_fifo_q  + 1 ;
--      else 
--        test_fifo_q <= (others=> '0');
--      end if;  
--    end if;
--  end if;
--end process;
--end test fifo reader      
  
AD1_PROCESS1:process(WREMPTY,RESET,AD_FIFO_RDCLOCK,WRFULL,AF,ae)
begin
    if RESET ='1' then
      AD_FLAG_TMP <='0';
    elsif rising_edge(AD_FIFO_RDCLOCK) then
      if WREMPTY = '1' or ae ='1' then
        AD_FLAG_TMP <='0';
      elsif WRFULL = '1'or af='1' then
        AD_FLAG_TMP <='1';
      else
        AD_FLAG_TMP <= AD_FLAG_TMP;
      end if;
    end if;
end process AD1_PROCESS1; 
AD1_DATA <= AD1_D_T;      
AD_FLAG(0) <= AD_FLAG_TMP;
END BLOCK AD1_CONTROL;
--========================================================--
AD2_CONTROL:block
  signal AD2_DATA_TEMP,AD2_D_T: std_logic_vector( 7 downto 0);
  signal AD2_FS,AD2_FIFO_RD: std_logic;
  signal WRFULL,WREMPTY: std_logic;
  signal AD_FLAG_TMP: std_logic;
  signal ae,af: std_logic;
  begin
  AD2_FIFO_RD <= AD_FIFO_RD and (not AD_FIFO_RDCS(1));
  
  AD2_COMPONENT: serial_ad
     port map (
          CLKADI => AD_CLK_2,
          CLR => RESET ,
          DAI => AD2_DATA_OUT ,
          NCS => AD2_CS_IN ,
          CS_OUT => adcs2,
          FLGO => AD2_FS ,
          DOUT => AD2_DATA_TEMP
        ); 
  AD2_FIFO_COMPONENT:fifo8x1024
    port map (
      WR_CS => adcs2,
      RD_CS =>AD_FIFO_RDCS(1),
      CLR => RESET,
      CLK => FF_CLOCK,
      RD=> AD2_FIFO_RD,
      WR => AD2_FS,
      DATA => AD2_DATA_TEMP,
      EMPTY => WREMPTY,
      FULL => WRFULL,
		af => af,
		ae => ae,
      Q => AD2_D_T
    );
  
AD2_PROCESS1:process(WREMPTY,RESET,AD_FIFO_RDCLOCK,WRFULL,AF,ae)
begin
    if RESET ='1' then
      AD_FLAG_TMP <='0';
    elsif rising_edge(AD_FIFO_RDCLOCK) then
      if WREMPTY = '1' or ae ='1'  then
        AD_FLAG_TMP <='0';
      elsif WRFULL = '1'or af='1' then
        AD_FLAG_TMP <='1';
      else
        AD_FLAG_TMP <= AD_FLAG_TMP;
      end if;
    end if;
end process AD2_PROCESS1; 
AD2_DATA <= AD2_D_T;
AD_FLAG(1) <= AD_FLAG_TMP;
END BLOCK AD2_CONTROL;


--========================================================--

AD3_CONTROL:block
  signal AD3_DATA_TEMP,AD3_D_T: std_logic_vector( 7 downto 0);
  signal AD3_FS: std_logic;
  signal WRFULL,WREMPTY,AD3_FIFO_RD : std_logic;
  signal AD_FLAG_TMP: std_logic;
  signal af,ae: std_logic;
  begin
  AD3_FIFO_RD <= AD_FIFO_RD and (not AD_FIFO_RDCS(2));
  AD3_COMPONENT: serial_ad
     port map (
          CLKADI => AD_CLK_2,
          CLR => RESET ,
          DAI => AD3_DATA_OUT ,
          NCS => AD3_CS_IN ,
          CS_OUT => adcs3,
          FLGO => AD3_FS ,
          DOUT => AD3_DATA_TEMP
        ); 
  AD3_FIFO_COMPONENT:fifo8x1024
    port map (
      WR_CS => adcs3,
      RD_CS =>AD_FIFO_RDCS(2),
      CLR => RESET,
      CLK => FF_CLOCK,
      RD=> AD3_FIFO_RD,
      WR => AD3_FS,
      DATA => AD3_DATA_TEMP,
      EMPTY => WREMPTY,
      FULL => WRFULL,
		af => af,
		ae => ae,
      Q => AD3_D_T
    );
  
AD3_PROCESS1:process(WREMPTY,RESET,AD_FIFO_RDCLOCK,WRFULL,AF,ae)
begin
    if RESET ='1' then
      AD_FLAG_TMP <='0';
    elsif rising_edge(AD_FIFO_RDCLOCK) then
      if WREMPTY = '1' or ae='1' then
        AD_FLAG_TMP <='0';
      elsif WRFULL = '1'or af='1' then
        AD_FLAG_TMP <='1';
      else
        AD_FLAG_TMP <= AD_FLAG_TMP;
      end if;
    end if;
end process AD3_PROCESS1; 
AD3_DATA <= AD3_D_T;
AD_FLAG(2) <= AD_FLAG_TMP;
END BLOCK AD3_CONTROL;


--========================================================--
AD4_CONTROL:block
  signal AD4_DATA_TEMP,AD4_D_T: std_logic_vector( 7 downto 0);
  signal AD4_FS: std_logic;
  signal WRFULL,WREMPTY,AD4_FIFO_RD : std_logic;
  signal AD_FLAG_TMP: std_logic;
  signal af,ae: std_logic;
  begin
  AD4_FIFO_RD <= AD_FIFO_RD and (not AD_FIFO_RDCS(3));
  
  AD4_COMPONENT: serial_ad
     port map (
          CLKADI => AD_CLK_2,
          CLR => RESET ,
          DAI => AD4_DATA_OUT ,
          NCS => AD4_CS_IN ,
          CS_OUT => adcs4,
          FLGO => AD4_FS ,
          DOUT => AD4_DATA_TEMP
        ); 
  AD4_FIFO_COMPONENT:fifo8x1024
    port map (
      WR_CS => adcs4,
      RD_CS =>AD_FIFO_RDCS(3),
      CLR => RESET,
      CLK => FF_CLOCK,
      RD=> AD4_FIFO_RD,
      WR => AD4_FS,
      DATA => AD4_DATA_TEMP,
      EMPTY => WREMPTY,
      FULL => WRFULL,
		af => af,
		ae => ae,
      Q => AD4_D_T
    );
  
AD4_PROCESS1:process(WREMPTY,RESET,AD_FIFO_RDCLOCK,WRFULL,AF,ae)
begin
    if RESET ='1' then
      AD_FLAG_TMP <='0';
    elsif rising_edge(AD_FIFO_RDCLOCK) then
      if WREMPTY = '1' or ae='1' then
        AD_FLAG_TMP <='0';
      elsif WRFULL = '1' or af='1' then
        AD_FLAG_TMP <='1';
      else
        AD_FLAG_TMP <= AD_FLAG_TMP;
      end if;
    end if;
end process AD4_PROCESS1; 
AD4_DATA <= AD4_D_T;           
AD_FLAG(3) <= AD_FLAG_TMP;
END BLOCK AD4_CONTROL;


--========================================================--
AD5_CONTROL:block
  signal AD5_DATA_TEMP,AD5_D_T: std_logic_vector( 7 downto 0);
  signal AD5_FS: std_logic;
  signal WRFULL,WREMPTY,AD5_FIFO_RD : std_logic;
  signal AD_FLAG_TMP: std_logic;
  signal ae,af: std_logic;
  begin
  AD5_FIFO_RD <= AD_FIFO_RD and (not AD_FIFO_RDCS(4));
  AD5_COMPONENT: serial_ad
     port map (
          CLKADI => AD_CLK_2,
          CLR => RESET ,
          DAI => AD5_DATA_OUT ,
          NCS => AD5_CS_IN ,
          CS_OUT => adcs5,
          FLGO => AD5_FS ,
          DOUT => AD5_DATA_TEMP
        ); 
  AD5_FIFO_COMPONENT:fifo8x1024
    port map (
      WR_CS => adcs5,
      RD_CS =>AD_FIFO_RDCS(4),
      CLR => RESET,
      CLK => FF_CLOCK,
      RD=> AD5_FIFO_RD,
      WR => AD5_FS,
      DATA => AD5_DATA_TEMP,
      EMPTY => WREMPTY,
      FULL => WRFULL,
		af => af,
      Q => AD5_D_T
    );
  
AD5_PROCESS1:process(WREMPTY,RESET,AD_FIFO_RDCLOCK,WRFULL,AF,ae)
begin
    if RESET ='1' then
      AD_FLAG_TMP <='0';
    elsif rising_edge(AD_FIFO_RDCLOCK) then
      if WREMPTY = '1' or ae='1' then
        AD_FLAG_TMP <='0';
      elsif WRFULL = '1' or af='1' then
        AD_FLAG_TMP <='1';
      else
        AD_FLAG_TMP <= AD_FLAG_TMP;
      end if;
    end if;
end process AD5_PROCESS1; 
AD5_DATA <= AD5_D_T;
AD_FLAG(4) <= AD_FLAG_TMP;
END BLOCK AD5_CONTROL;
end a;