fifo12x1024c.vhd

VHDL语言的ADDA（模数数模置换）控制

---------------------------------------------------------------------------------------------------
--		    
-- Title       : fifo12x1024
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
---------------------------------------------------------------------------------------------------
--
-- File        : fifo12x1024.vhd
-- Generated   : Tue Nov  4 13:37:53 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------
--
-- Assume parameters Delay_RdUsedW, Delay_WrUsedW, RdSync_DelayPipe, and
--     WrSync_DelayPipe to be all 0.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity fifo12x1024c is
	port(
		WR_CS : in std_logic;   --ACTIVE '0'
		RD_CS : in std_logic; --ACTIVE '0'
		CLR : in std_logic; --ACTIVE '1'
		CLK : in std_logic;
		RD : in std_logic; --ACTIVE '1'
		WR : in std_logic; --ACTIVE '1'
		DATA : in std_logic_vector (11 downto 0);
		EMPTY : out std_logic; --ACTIVE '1'
		FULL : out std_logic; --ACTIVE '1'
		AE : out std_logic; --ACTIVE '1'
		AF : out std_logic; --ACTIVE '1'
		Q : out std_logic_vector (11 downto 0)
	);	  
end fifo12x1024c;

architecture fifo_arch of fifo12x1024c is

type fifo12x1024_array_type is array (15 downto 0) of std_logic_vector (11 downto 0);
signal fifo12x1024_array : fifo12x1024_array_type;
signal WR_PTR : INTEGER range 0 to 15;
signal RD_PTR : INTEGER range 0 to 15;
signal WR_TMP,RD_TMP,WR_TEMP,WR_TT,wr_ttt : std_logic;		 -- RD_TEMP,
signal T1,T2,T3,T4: std_logic;
signal Q_TMP : std_logic_vector(11 downto 0);
signal FULL_TMP, EMPTY_TMP : std_logic;
begin
FULL <= FULL_TMP;
EMPTY <= EMPTY_TMP;
	process (CLR, CLK)
	begin
		if CLR = '1' then
			for INDEX in 15 downto 0 loop
				fifo12x1024_array(INDEX) <= (others => '0');
			end loop;
		elsif rising_edge(CLK) then
				if (WR_TEMP = '1' and FULL_TMP = '0' AND WR_CS = '0') then
					fifo12x1024_array(WR_PTR) <= DATA;
				end if;
		end if;
	end process;

	process (CLR, CLK)
		variable PTR : INTEGER range 0 to 16;
	begin
		if CLR = '1' then
			WR_PTR <= 0;
			RD_PTR <= 0;
			EMPTY_TMP <= '1';
			FULL_TMP <= '0';
			AE <= '0';
			AF <= '0';
			PTR := 0;
		elsif rising_edge(CLK) then
				if ( WR_TEMP = '1' and WR_CS='0' and PTR < 16 )then
					if WR_PTR < 15 then
						WR_PTR <= WR_PTR + 1;
					elsif WR_PTR = 15 then
						WR_PTR <= 0;
					end if;
					PTR := PTR + 1;
				elsif ( RD_TMP = '1' and PTR > 0 and RD_CS ='0' )then  -- 
					if RD_PTR < 15 then
						RD_PTR <= RD_PTR + 1;
					elsif RD_PTR = 15 then
						RD_PTR <= 0;
					end if;
					PTR := PTR - 1;
				end if;

				if PTR = 0 then
					EMPTY_TMP <= '1';
				else
					EMPTY_TMP <= '0';
				end if;

				if PTR = 16 then
					FULL_TMP<= '1';
				else
					FULL_TMP <= '0';
				end if;

				if PTR > 0 and PTR <= 2 then
					AE <= '1';
				else
					AE <= '0';
				end if;

				if PTR < 16 and PTR >= 13 then
					AF <= '1';
				else
					AF <= '0';
				end if;
			end if;

	end process;
	process (CLK,CLR,RD_TMP)
	begin
		if CLR='1' then
			Q_TMP <=(others=>'0');
		elsif rising_edge(CLK) then
			if (RD_TMP = '1' AND EMPTY_TMP = '0'and RD_CS ='0') then
				Q_TMP <= fifo12x1024_array(RD_PTR);  
			else
				Q_TMP <= Q_TMP ;   
			end if;
		end if;
	end process;
	Q<=Q_TMP;
P1:	process(CLK,CLR,WR_CS)
	begin
		if CLR ='1' or WR_CS ='1' then
			T1<='0';
			T2<='0';
		elsif falling_edge(clk)THEN
			T1<=WR;
		    if WR='1' and T1= '0'then
				T2<='1';
			else
				T2<='0';
			end if;
		END IF;	
	END PROCESS P1;
			WR_TMP<=T2;
P4: process(clk,clr)
begin
	if clr ='1' then
		WR_TT <='0';
	elsif falling_edge (clk) then
		WR_TT <= WR_TMP;
	end if;
end process P4;
P5: process(clk,clr)
begin
	if clr ='1' then
		wr_ttt <='0';
	elsif falling_edge (clk) then
		wr_ttt <= WR_TT;
	end if;
end process P5;

P6 :process (clk,clr)
begin
	if clr= '1' then
		WR_TEMP <='0';
	elsif falling_edge (clk) then
		WR_TEMP <= WR_TTT;
	end if;
end process P6;


P2:	process(CLK,CLR)
	begin
		if CLR ='1'then
			T3<='0';
			T4<='0';
		elsif falling_edge(clk) THEN
			T3<=RD;--_TEMP;
		    if RD='1' and T3= '0'then
				T4<='1';
			else
				T4<='0';
			end if;
		END IF;	
	END PROCESS P2;
	RD_TMP<=T4;
--P3:	process(CLK,RD_CS,CLR)
--	begin
--		if CLR = '1' then
--			RD_TEMP <='0';
--		elsif RD_CS ='0' then
--			RD_TEMP<=RD;
--		else
--			RD_TEMP <= '0';
--		end if;
--	end process P3;
end fifo_arch;