dsp_port.vhd

程控交换机芯片用的VHDL语言程序, 与DSP配合完成程控交换机功能

      );

GCLK_UUT3: IBUFG 
port map (
      I => TR_BR_IN, 
      O => TR_BR
      );

rstpad : IBUF   
port map (
      I=>RST_IN, 
      O=>RST);

DSP_RW_UUT: IBUF 
port map (
      I => DSP_RW, 
      O=> RW);


INSERT_MEM_CONTROL: mem_control
port map(
        MSTRB =>MSTRB,
        A19 =>A(19),
        PS =>PS,
        RW =>RW,
        DS =>DS,
        XF => XF,
        SRAM_CE =>SRAM_CE,
        SRAM_WE =>SRAM_WE,
        SRAM_OE =>SRAM_OE,
        FLASH_CE =>FLASH_CE,
        FLASH_WE =>FLASH_WE_TMP,
        FLASH_OE =>FLASH_OE
        );
FLASH_WE <= FLASH_WE_EN or FLASH_WE_TMP or XF;
end block DATA_BUS_CONNECTION;

--========================================================--
--SELECT IO SPACE
IO_SELECT:BLOCK
begin
INSERT_SYSTEM_IO: system_io
port map (
  DSPIS =>DSPIS,
  RW =>RW,
  A => A(19 downto 0),
  FLAG_BLOCK_DATA =>FLAG_BLOCK_DATA,
  AD1_DATA =>AD1_DATA,
  AD2_DATA =>AD2_DATA,
  AD3_DATA =>AD3_DATA,
  AD4_DATA =>AD4_DATA,
  AD5_DATA =>AD5_DATA,
  KEY_DATA =>KEY_DATA,
  DSP_DATA_OUT =>DSP_DATA_OUT,
  SYSTEM_FLAG2_DATA => SYSTEM_FLAG2_DATA,
  DA_DATA_TEMP =>DA_DATA_TEMP,
  KEY_CS =>KEY_CS,
  IC2_TR =>IC2_TR,
  LCD_RAM_CS =>LCD_RAM_CS,
  AD_FIFO_RDCS =>AD_FIFO_RDCS,
  DA_BLOCK_CS =>DA_BLOCK_CS,
  PCM_USER_INFO_CS =>PCM_USER_INFO_CS,
  EXCHANGE_MOD_CS =>EXCHANGE_MOD_CS,
  USER_RING_CONTROL_CS =>USER_RING_CONTROL_CS,
  ss7tx_fifo_cs => ss7tx_fifo_cs,
  ss7rx_fifo_cs => ss7rx_fifo_cs,
  ss7_data_out => ss7_data_out,
  uart_data_out => uart_data_out,
  uart_tx_fifo_wrcs =>  uart_tx_fifo_wrcs,
  uart_rx_fifo_rdcs => uart_rx_fifo_rdcs

);
 
 

END BLOCK IO_SELECT;
--========================================================--
FLAG_BLOCK: BLOCK
begin
INSERT_SYSTEM_FLAG : system_flag
port map(
  LCD_RAM_FLAG =>LCD_RAM_RD_OVER,
  EXT_RING_STA =>EXT_STA_TMP,
  SHK_TMP =>SHK_TMP,
  DA_FLAG =>DA_FLAG,
  AD_FLAG =>AD_FLAG,
  KEY_FLAG =>KEY_FLAG,
  DSP_CLK => DSP_CLKOUT,
  CLR => CLR,
  KEY_CS =>KEY_CS,
  KEY_FLAG_CLR =>KEY_FLAG_CLR,
  FLAG_BLOCK_DATA =>FLAG_BLOCK_DATA
  );

INSERT_SYSTEM_FLAG2: SYSTEM_FLAG2
port map
(
    sta1 => uart_tx_busy,
    sta2 => connect_pc_tmp,
    sta3 => ss7_tx_busy,
    sta4 => ss7_rx_rdy,
    SYSTEM_FLAG2_DATA => SYSTEM_FLAG2_DATA
) ;
end block FLAG_BLOCK;


--========================================================--
--key board  
--INSERT KEY_CONTROL 
KEY_BLOCK: block
begin
INSERT_KEY_CONTROL: key_control  
port map(
    KEY => KEY,
    SCAN_CLK => CLK_128K, --128K
    KEY_FLAG_CLR => KEY_FLAG_CLR,
    CLR => CLR,
    KEY_FLAG => KEY_FLAG,
    KEY_DATA => KEY_DATA
  );

end block KEY_BLOCK;

--========================================================--

LCD_CONTROL:BLOCK
signal BUS_CTL: std_logic;
BEGIN
INSERT_LCD_PORT : lcd_port
port map(
      LCD_CLK => clk_480k,--1024K, 
      DSP_CLK => DSP_CLKOUT, --100MHz
      CLR => CLR,
      DSP_RW => RW,
      LCD_RAM_CS => LCD_RAM_CS,
      DSP_ADDRESS => A(11 downto 0),
      LCD_DIN => LCD_DIN,
      BUS_CTL_OUT => BUS_CTL,
      LCD_DOUT => LCD_DOUT,
      LCD_RD_O => LCD_RD_TEMP,
      LCD_WR_O => LCD_WR_TEMP,
      LCD_CE_O => LCD_CE_TEMP,
      LCD_CD_O => LCD_CD_TEMP,
--      LCD_RST_O => LCD_RST_TEMP,
      EXT_RAM_WE_O => EXT_RAM_WR_TMP,
      EXT_RAM_OE_O => EXT_RAM_OE_TMP,
      EXT_RAM_CE_O => EXT_RAM_CE_TMP,
      EXT_RAM_A_O => EXT_RAM_A( 11 downto 0),
      EXT_RAM_D_IN => EXT_RAM_D_IN,
      LCD_RAM_RD_OVER => LCD_RAM_RD_OVER
    );

   --LCD_FS_TEMP <='0';
     LCD_RD <= LCD_RD_TEMP;
     LCD_WR <= LCD_WR_TEMP;
     LCD_CE <= LCD_CE_TEMP;
     LCD_CD <= LCD_CD_TEMP;
   --LCD_FS <= LCD_FS_TEMP;
     LCD_RST <= rst;-- LCD_RST_TEMP;
     LCD_D <= LCD_DOUT when (LCD_WR_TEMP ='0' and LCD_RD_TEMP ='1') else (others =>'Z');
     LCD_DIN <= LCD_D when ( LCD_RD_TEMP ='0' and LCD_WR_TEMP ='1') else LCD_DIN;
     U38_OE1 <= '0';
     U38_OE2 <= '0';
     U38_TR1 <= not LCD_WR_TEMP;
     U38_TR2 <= '1';

     EXT_RAM_WR <= EXT_RAM_WR_TMP;
     EXT_RAM_CE <= EXT_RAM_CE_TMP;
     EXT_RAM_OE <= EXT_RAM_OE_TMP;
     EXT_RAM_A(14 downto 12 ) <= ( others => '0');
     EXT_RAM_D_IN <= EXT_RAM_D when ( EXT_RAM_OE_TMP ='0' and EXT_RAM_CE_TMP = '0') else EXT_RAM_D_IN;
     EXT_RAM_D <= DSP_DATA_IN( 7 downto 0) when ( EXT_RAM_OE_TMP ='1' and EXT_RAM_CE_TMP = '0' and EXT_RAM_WR_TMP ='0' ) else (others => 'Z'); 

END BLOCK LCD_CONTROL;

--========================================================--
--AD_control
--INSERT AD_CONTROL 
AD_BLOCK: block

component ad_control
  port(  CLK_AD : in std_logic; --256K 
         AD_CLK : out std_logic;
         RESET : in std_logic;
--AD1
         AD1_DATA_OUT : in std_logic;
         AD1_CS_IN : in std_logic;
         AD1_CS_OUT : out std_logic;
         AD1_DATA : out std_logic_vector(7 downto 0);

--AD2
         AD2_DATA_OUT : in std_logic;
         AD2_CS_IN : in std_logic;
         AD2_CS_OUT : out std_logic;
         AD2_DATA : out std_logic_vector(7 downto 0);
--AD3   
         AD3_DATA_OUT : in std_logic;
         AD3_CS_IN : in std_logic;
         AD3_CS_OUT : out std_logic;
         AD3_DATA : out std_logic_vector(7 downto 0);
--AD4
         AD4_DATA_OUT : in std_logic;
         AD4_CS_IN : in std_logic;
         AD4_CS_OUT : out std_logic;     
         AD4_DATA : out std_logic_vector(7 downto 0);
--AD5
         AD5_DATA_OUT : in std_logic;
         AD5_CS_IN : in std_logic;
         AD5_CS_OUT : out std_logic;
         
         AD5_DATA : out std_logic_vector(7 downto 0);
--       AD_FLAG_CLR : in std_logic_vector(4 downto 0);
         AD_FIFO_RDCLOCK : in std_logic;
         AD_FIFO_RD : in std_logic;
         AD_FIFO_RDCS : in std_logic_vector(4 downto 0);
         AD_FLAG : out std_logic_vector(4 downto 0));
end component;
signal AD_CLK : std_logic;
begin
INSERT_AD_CONTROL: ad_control 
port map (
       CLK_AD => CLK_160K,
       AD_CLK => AD_CLK,
       RESET => CLR,
--AD1
       AD1_DATA_OUT => AD1_OUT,
       AD1_CS_IN => START_AD1,
       AD1_CS_OUT => AD1_CS,
       AD1_DATA => AD1_DATA,
--AD2
       AD2_DATA_OUT => AD2_OUT,
       AD2_CS_IN => START_AD2,
       AD2_CS_OUT => AD2_CS,
       AD2_DATA => AD2_DATA,
--AD3   
       AD3_DATA_OUT => AD3_OUT,
       AD3_CS_IN => START_AD3,
       AD3_CS_OUT => AD3_CS,
       AD3_DATA => AD3_DATA,
--AD4
       AD4_DATA_OUT => AD4_OUT,
       AD4_CS_IN => START_AD4,
       AD4_CS_OUT => AD4_CS,
       AD4_DATA => AD4_DATA,
--AD5
       AD_FIFO_RDCLOCK =>  DSP_CLKOUT,
       AD_FIFO_RD => RW,
       AD_FIFO_RDCS => AD_FIFO_RDCS,

       AD5_DATA_OUT => AD5_OUT,
       AD5_CS_IN => START_AD5,
       AD5_CS_OUT => AD5_CS,
       AD5_DATA => AD5_DATA,
--       AD_FLAG_CLR => AD_FLAG_CLR,
       AD_FLAG => AD_FLAG
    );

  CLK_AD<= AD_CLK;
  START_AD1 <=  SHK_TMP(0);
  START_AD2 <=  SHK_TMP(1);
  START_AD3 <=  SHK_TMP(2);
  START_AD4 <=  SHK_TMP(3);
  START_AD5 <=  EXT_RING_DETECTED;
end block AD_BLOCK;
--========================================================--

INSERT_DA_CONTROL:BLOCK

component da_control
port(  
    DATA : in std_logic_vector( 15 downto 0);
    DA_CLK,FIFO_WRCLK : in std_logic;--256K    
    WR : in std_logic;
    CLR : in std_logic;
    DA_FF_CS : in std_logic_vector( 3 downto 0);
    DA_FF_FULL : out std_logic_vector ( 3 downto 0);
    DA_DATA : out std_logic_vector( 1 downto 0);
    DA_CLK_OUT : out std_logic_vector( 1 downto 0);
    DA_LD_OUT : out std_logic_vector( 1 downto 0)

);
end component ;
signal DA_CLK_TMP : std_logic_vector(1 downto 0);
signal DA_CS_TMP : std_logic_vector( 1 downto 0);
signal DA_DIN_TMP : std_logic_vector(1 downto 0);
BEGIN
INSERT_DABLOCK: da_control
port map(  
    DATA =>DSP_DATA_IN,--DA_DATA_TEMP,
    DA_CLK =>clk_480k,--256K,  
    WR => RW,
    CLR =>CLR ,
    DA_FF_CS => DA_BLOCK_CS, 
    DA_FF_FULL => DA_FLAG,
    DA_DATA => DA_DIN_TMP,
    DA_CLK_OUT => DA_CLK_TMP,
    DA_LD_OUT => DA_CS_TMP,
--    FFA_DOUT => FFA_D_TMP,    --TEST
    FIFO_WRCLK => DSP_CLKOUT
);
DA_CLK<=DA_CLK_TMP;
DA_DIN<=DA_DIN_TMP;
DA_CS<=DA_CS_TMP;
END BLOCK INSERT_DA_CONTROL;

--========================================================--

PCM_CONTROL:BLOCK

signal pcm_at_tmp,pcm_bt_tmp,pcm_ct_tmp,pcm_dt_tmp,pcm_et_tmp:std_logic;
signal pcm_ar_tmp,pcm_br_tmp,pcm_cr_tmp,pcm_dr_tmp,pcm_er_tmp:std_logic;
signal PCM_FS0 : std_logic;
signal pcm_bs_tmp : std_logic;

BEGIN

pcm_at_tmp <= not pcm_at;
pcm_bt_tmp <= not pcm_bt;
pcm_ct_tmp <= not pcm_ct;
pcm_dt_tmp <= not pcm_dt;
pcm_et_tmp <= not pcm_et;
pcm_ar <= not pcm_ar_tmp;
pcm_br <= not pcm_br_tmp;
pcm_cr <= not pcm_cr_tmp;
pcm_dr <= not pcm_dr_tmp;
pcm_er <= not pcm_er_tmp;

INSERT_PCM_EXCHANGE: pcm_exchange
  port map (
    DSP_DATA_IN => DSP_DATA_IN,
    SYS_CLK => SYS_CLK,
    CLK_100M => DSP_CLKOUT,
    RW =>RW,
    CLR => CLR,
    EXCHANGE_MOD_CS => EXCHANGE_MOD_CS,
    PCM_USER_INFO_CS => PCM_USER_INFO_CS,
    PCM_AT => pcm_at_tmp,
    PCM_BT => pcm_bt_tmp,
    PCM_CT => pcm_ct_tmp,
    PCM_DT => pcm_dt_tmp,     
    PCM_ET => pcm_et_tmp,
    PCM_AR => pcm_ar_tmp,
    PCM_BR => pcm_br_tmp,
    PCM_CR => pcm_cr_tmp,
    PCM_DR => pcm_dr_tmp,
    PCM_ER => pcm_er_tmp,
    FS_AR => FS_AR,
    FS_BR => FS_BR,
    FS_CR => FS_CR,
    FS_DR => FS_DR,
    FS_ER => FS_ER,
    FS_AT => FS_AT,
    FS_BT => FS_BT,
    FS_CT => FS_CT,
    FS_DT => FS_DT,
    FS_ET => FS_ET,
    PCM_BS => pcm_bs_tmp,

    ss7_data_out => ss7_data_out,
    ss7tx_fifo_cs => ss7tx_fifo_cs,
    ss7rx_fifo_cs => ss7rx_fifo_cs,
    ss7_tx_busy => ss7_tx_busy,
    ss7_rx_rdy => ss7_rx_rdy,

    TR_PCMX => TR_PCMX,
    TR_BX => TR_BX,
    TR_PCMR => TR_PCMR,
    TR_BR => TR_BR,
    ss7_txd => ss7_txd,-- FX
    ss7_rxd => ss7_rxd,-- FR

--    CLK_8192K_OUT => CLK_8192K,
--    CLK_4096K_OUT => CLK_4096K,
--    CLK_2048K_OUT => CLK_2048K,
--    CLK_1024K_OUT => CLK_1024K,
--    CLK_512K_OUT => CLK_512K,
--    CLK_256K_OUT => CLK_256K,
    CLK_128K_OUT => CLK_128K,
    CLK_64K_OUT => CLK_64K

--    RELAY => RELAY
  );
    PCM_BS <= pcm_bs_tmp;
 --   TR_PCMX <= PCM_B; 
--    TR_FX <= PCM_FS0;
--    TR_BX <= pcm_bs_tmp;

END BLOCK PCM_CONTROL;

USER_STA_BLOCK : block 
signal M1_SHK_TMP,M2_SHK_TMP,M3_SHK_TMP,M4_SHK_TMP : std_logic;
begin
INSERT_USER_STA : user_sta
  port map (
     CLK_256K => CLK_64K,
   --  CLK_64K => CLK_64K,
     CLR => CLR,
     M1_SHK =>M1_SHK_TMP,
     M2_SHK =>M2_SHK_TMP,
     M3_SHK =>M3_SHK_TMP,
     M4_SHK =>M4_SHK_TMP,
   --  RING_D =>RING_D,
     SHK_TMP => SHK_TMP
   --  EXT_RING_STA => EXT_RING_STA
  );
M1_SHK_TMP <= not M1_SHK;
M2_SHK_TMP <= not M2_SHK;
M3_SHK_TMP <= not M3_SHK;
M4_SHK_TMP <= not M4_SHK;

end block USER_STA_BLOCK;


USER_RING_CONTROL: block 
begin
INSERT_USER_CONTROL: user_ring
  port map (
  CLR => CLR,
  RW => RW,
  USER_RING_CONTROL_CS => USER_RING_CONTROL_CS,
  DSP_DATA_IN =>DSP_DATA_IN,
  USER_RC  => USER_RC,
  PASSC =>PASSC_TMP
  );
PASSC<=PASSC_TMP;
end block USER_RING_CONTROL;

INSERT_EXT_RING_DETECTED: block 
begin
EXT_RING_DETECT: ext_ring_dete
port map (
  CLK => CLK_128K,
  PASSC_TMP => PASSC_TMP,
  EXT_STA => EXT_STA_TMP,
  CLR => CLR,
  RING_D => RING_D,
  EXT_RING_DETECTED => EXT_RING_DETECTED
  );

end block INSERT_EXT_RING_DETECTED;

communication_uart_i2c:block
component communication 
    port(
          clr: in std_logic;
          clk_uart: in std_logic;     --100M: 115200bps
          txd : out std_logic;
          rxd: in std_logic;
          uart_data_in : in std_logic_vector(7 downto 0);
          uart_data_out : out std_logic_vector(7 downto 0);
          uart_int:out std_logic;
          connect_pc : out std_logic;
          uart_tx_busy : out std_logic;
          uart_tx_fifo_wrcs : in std_logic;
          uart_rx_fifo_rdcs : in std_logic;
    -- dsp connection port
          dsp_rw: in std_logic  
);
end component;
begin
insert_communication: communication
port map(
          clr => clr,
          clk_uart => DSP_CLKOUT,
          txd => txd,
          rxd => rxd,
          uart_data_in => DSP_DATA_IN( 7 downto 0),
          uart_data_out => uart_data_out,
          connect_pc => connect_pc_tmp,
          uart_tx_busy => uart_tx_busy,
          uart_int => uart_int,
          uart_tx_fifo_wrcs =>  uart_tx_fifo_wrcs,
          uart_rx_fifo_rdcs => uart_rx_fifo_rdcs,
    -- dsp connection port
          dsp_rw => rw
);
connect_pc <= not connect_pc_tmp;
end block communication_uart_i2c;

--test
--TEST(4 DOWNTO 0) <= TEST_TMP(7 DOWNTO 3);
--TEST(1) <= AD1_DATA(1);
--TEST(2) <= AD1_DATA(2);
--key_cs_out <= AD1_DATA(3);
--bus_ctl_out <= AD1_DATA(4);

clk_gen:block

--signal cta : integer range 0 to 34;
--signal ctb : std_logic_vector(1 downto 0);

begin
clk_gen_uut1: clk_gen_block
    Port map ( 
           dsp_clk_in => DSP_CLKOUT,
           clr => clr,
           dsp_clk_divout => dsp_clk_divout,
           clk_480k => clk_480k,
           clk_160k => clk_160k
    ); 
end block clk_gen;
end a;