eight.vhd

来自「用VHDL写的一个8位全加器的实验程序,供新手参考」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity eight is
port(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7:in std_logic;
	 	s0,s1,s2,s3,s4,s5,s6,s7:out std_logic;
	 	c1,c2,c3,c4,c5,c6,c7:buffer std_logic);
end entity eight;
architecture one of eight is
begin
		s0<=(a0 xor b0); c1<=a0 and b0;
		s1<=(a1 xor b1) xor c1; c2<=(a1 and b1) or (a1 and c1) or (b1 and c1);
		s2<=(a2 xor b2) xor c2; c3<=(a2 and b2) or (a2 and c2) or (b2 and c2);
		s3<=(a3 xor b3) xor c3; c4<=(a3 and b3) or (a3 and c3) or (b3 and c3);
		s4<=(a4 xor b4) xor c4; c5<=(a4 and b4) or (a4 and c4) or (b4 and c4);
		s5<=(a5 xor b5) xor c5; c6<=(a5 and b5) or (a5 and c5) or (b5 and c5);
		s6<=(a6 xor b6) xor c6; c7<=(a6 and b6) or (a6 and c6) or (b6 and c6);
		s7<=(a7 xor b7) xor c7; 	
end architecture one;