ch8_5.vhd

来自「用VHDL写的一个5/8分频器,希望对刚学习VHDL的朋友有帮助」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CH8_5 IS
PORT(CP:IN STD_LOGIC;
	 OP:OUT STD_LOGIC);
END;
ARCHITECTURE a OF Ch8_5 IS
SIGNAL  DLY: STD_LOGIC;
SIGNAL 	QN :STD_LOGIC_VECTOR(3 DOWNTO 0);   
BEGIN
     PROCESS (CP)
     BEGIN
           IF CP'event AND CP='1' THEN
	DLY <= QN(3);
	QN <= QN + 5; 
           END IF;     
     END PROCESS;			
     OP<=(QN(3) Xor DLY) And (Not CP);		
END a;