lcd_1602.tan.summary

来自「1602 LCD控制的verilog代码」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.019 ns
From           : reset
To             : lcd:inst|clkcnt[19]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 28.145 ns
From           : lcd:inst|data[6]
To             : lcd_data[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 17.605 ns
From           : reset
To             : lcd:inst|data[7]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 68.70 MHz ( period = 14.555 ns )
From           : lcd:inst|counter[2]
To             : lcd:inst|address[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lcd:inst|clk_int
To             : lcd:inst|clk_int
From Clock     : clk
To Clock       : clk
Failed Paths   : 183

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 183

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