prev_cmp_eda.map.qmsg

能够产生方波、三角波、正弦波、及阶梯波

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ladder ladder:u4 " "Info: Elaborating entity \"ladder\" for hierarchy \"ladder:u4\"" {  } { { "EDA.vhd" "u4" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "setfun setfun:u5 " "Info: Elaborating entity \"setfun\" for hierarchy \"setfun:u5\"" {  } { { "EDA.vhd" "u5" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ladder:u4\|i\[0\] data_in GND " "Warning (14130): Reduced register \"ladder:u4\|i\[0\]\" with stuck data_in port to stuck value GND" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "square:u3\|i\[0\] data_in GND " "Warning (14130): Reduced register \"square:u3\|i\[0\]\" with stuck data_in port to stuck value GND" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 15 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "delta:u2\|i\[0\] data_in GND " "Warning (14130): Reduced register \"delta:u2\|i\[0\]\" with stuck data_in port to stuck value GND" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 14 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sin:u1\|i\[0\] data_in GND " "Warning (14130): Reduced register \"sin:u1\|i\[0\]\" with stuck data_in port to stuck value GND" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 14 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ladder:u4\|tmp\[1\] data_in GND " "Warning (14130): Reduced register \"ladder:u4\|tmp\[1\]\" with stuck data_in port to stuck value GND" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 37 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ladder:u4\|tmp\[0\] data_in GND " "Warning (14130): Reduced register \"ladder:u4\|tmp\[0\]\" with stuck data_in port to stuck value GND" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 37 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ladder:u4\|tmp\[2\] data_in GND " "Warning (14130): Reduced register \"ladder:u4\|tmp\[2\]\" with stuck data_in port to stuck value GND" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 37 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ladder:u4\|tmp\[3\] data_in GND " "Warning (14130): Reduced register \"ladder:u4\|tmp\[3\]\" with stuck data_in port to stuck value GND" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 37 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|tem\[0\] ladder:u4\|tem\[0\] " "Info (13350): Duplicate register \"sin:u1\|tem\[0\]\" merged to single register \"ladder:u4\|tem\[0\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|tem\[0\] ladder:u4\|tem\[0\] " "Info (13350): Duplicate register \"delta:u2\|tem\[0\]\" merged to single register \"ladder:u4\|tem\[0\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|tem\[0\] ladder:u4\|tem\[0\] " "Info (13350): Duplicate register \"square:u3\|tem\[0\]\" merged to single register \"ladder:u4\|tem\[0\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 26 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|tem\[1\] ladder:u4\|tem\[1\] " "Info (13350): Duplicate register \"sin:u1\|tem\[1\]\" merged to single register \"ladder:u4\|tem\[1\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|tem\[1\] ladder:u4\|tem\[1\] " "Info (13350): Duplicate register \"delta:u2\|tem\[1\]\" merged to single register \"ladder:u4\|tem\[1\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|tem\[1\] ladder:u4\|tem\[1\] " "Info (13350): Duplicate register \"square:u3\|tem\[1\]\" merged to single register \"ladder:u4\|tem\[1\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 26 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|tem\[2\] ladder:u4\|tem\[2\] " "Info (13350): Duplicate register \"sin:u1\|tem\[2\]\" merged to single register \"ladder:u4\|tem\[2\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|tem\[2\] ladder:u4\|tem\[2\] " "Info (13350): Duplicate register \"delta:u2\|tem\[2\]\" merged to single register \"ladder:u4\|tem\[2\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|tem\[2\] ladder:u4\|tem\[2\] " "Info (13350): Duplicate register \"square:u3\|tem\[2\]\" merged to single register \"ladder:u4\|tem\[2\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 26 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|tem\[3\] ladder:u4\|tem\[3\] " "Info (13350): Duplicate register \"sin:u1\|tem\[3\]\" merged to single register \"ladder:u4\|tem\[3\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|tem\[3\] ladder:u4\|tem\[3\] " "Info (13350): Duplicate register \"delta:u2\|tem\[3\]\" merged to single register \"ladder:u4\|tem\[3\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|tem\[3\] ladder:u4\|tem\[3\] " "Info (13350): Duplicate register \"square:u3\|tem\[3\]\" merged to single register \"ladder:u4\|tem\[3\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 26 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|tem\[4\] ladder:u4\|tem\[4\] " "Info (13350): Duplicate register \"sin:u1\|tem\[4\]\" merged to single register \"ladder:u4\|tem\[4\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|tem\[4\] ladder:u4\|tem\[4\] " "Info (13350): Duplicate register \"delta:u2\|tem\[4\]\" merged to single register \"ladder:u4\|tem\[4\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 25 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|tem\[4\] ladder:u4\|tem\[4\] " "Info (13350): Duplicate register \"square:u3\|tem\[4\]\" merged to single register \"ladder:u4\|tem\[4\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 26 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|i\[1\] ladder:u4\|i\[1\] " "Info (13350): Duplicate register \"sin:u1\|i\[1\]\" merged to single register \"ladder:u4\|i\[1\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|i\[1\] ladder:u4\|i\[1\] " "Info (13350): Duplicate register \"delta:u2\|i\[1\]\" merged to single register \"ladder:u4\|i\[1\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|i\[1\] ladder:u4\|i\[1\] " "Info (13350): Duplicate register \"square:u3\|i\[1\]\" merged to single register \"ladder:u4\|i\[1\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 15 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|i\[2\] ladder:u4\|i\[2\] " "Info (13350): Duplicate register \"sin:u1\|i\[2\]\" merged to single register \"ladder:u4\|i\[2\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|i\[2\] ladder:u4\|i\[2\] " "Info (13350): Duplicate register \"delta:u2\|i\[2\]\" merged to single register \"ladder:u4\|i\[2\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|i\[2\] ladder:u4\|i\[2\] " "Info (13350): Duplicate register \"square:u3\|i\[2\]\" merged to single register \"ladder:u4\|i\[2\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 15 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|i\[3\] ladder:u4\|i\[3\] " "Info (13350): Duplicate register \"sin:u1\|i\[3\]\" merged to single register \"ladder:u4\|i\[3\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|i\[3\] ladder:u4\|i\[3\] " "Info (13350): Duplicate register \"delta:u2\|i\[3\]\" merged to single register \"ladder:u4\|i\[3\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|i\[3\] ladder:u4\|i\[3\] " "Info (13350): Duplicate register \"square:u3\|i\[3\]\" merged to single register \"ladder:u4\|i\[3\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 15 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sin:u1\|i\[4\] ladder:u4\|i\[4\] " "Info (13350): Duplicate register \"sin:u1\|i\[4\]\" merged to single register \"ladder:u4\|i\[4\]\"" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "delta:u2\|i\[4\] ladder:u4\|i\[4\] " "Info (13350): Duplicate register \"delta:u2\|i\[4\]\" merged to single register \"ladder:u4\|i\[4\]\"" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 14 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "square:u3\|i\[4\] ladder:u4\|i\[4\] " "Info (13350): Duplicate register \"square:u3\|i\[4\]\" merged to single register \"ladder:u4\|i\[4\]\"" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 15 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "121 " "Info: Implemented 121 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "110 " "Info: Implemented 110 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "178 " "Info: Peak virtual memory: 178 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 05 11:55:40 2009 " "Info: Processing ended: Mon Jan 05 11:55:40 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}