eda.tan.qmsg

能够产生方波、三角波、正弦波、及阶梯波

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "fqset register register ladder:u4\|i\[3\] ladder:u4\|i\[2\] 275.03 MHz Internal " "Info: Clock \"fqset\" Internal fmax is restricted to 275.03 MHz between source register \"ladder:u4\|i\[3\]\" and destination register \"ladder:u4\|i\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.549 ns + Longest register register " "Info: + Longest register to register delay is 1.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ladder:u4\|i\[3\] 1 REG LC_X38_Y13_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y13_N5; Fanout = 5; REG Node = 'ladder:u4\|i\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ladder:u4|i[3] } "NODE_NAME" } } { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.738 ns) 1.549 ns ladder:u4\|i\[2\] 2 REG LC_X38_Y13_N8 5 " "Info: 2: + IC(0.811 ns) + CELL(0.738 ns) = 1.549 ns; Loc. = LC_X38_Y13_N8; Fanout = 5; REG Node = 'ladder:u4\|i\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.549 ns" { ladder:u4|i[3] ladder:u4|i[2] } "NODE_NAME" } } { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 47.64 % ) " "Info: Total cell delay = 0.738 ns ( 47.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.811 ns ( 52.36 % ) " "Info: Total interconnect delay = 0.811 ns ( 52.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.549 ns" { ladder:u4|i[3] ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.549 ns" { ladder:u4|i[3] {} ladder:u4|i[2] {} } { 0.000ns 0.811ns } { 0.000ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fqset destination 3.178 ns + Shortest register " "Info: + Shortest clock path from clock \"fqset\" to destination register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fqset 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'fqset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fqset } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns ladder:u4\|i\[2\] 2 REG LC_X38_Y13_N8 5 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X38_Y13_N8; Fanout = 5; REG Node = 'ladder:u4\|i\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { fqset ladder:u4|i[2] } "NODE_NAME" } } { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[2] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fqset source 3.178 ns - Longest register " "Info: - Longest clock path from clock \"fqset\" to source register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fqset 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'fqset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fqset } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns ladder:u4\|i\[3\] 2 REG LC_X38_Y13_N5 5 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X38_Y13_N5; Fanout = 5; REG Node = 'ladder:u4\|i\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { fqset ladder:u4|i[3] } "NODE_NAME" } } { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[3] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[2] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[3] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.549 ns" { ladder:u4|i[3] ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.549 ns" { ladder:u4|i[3] {} ladder:u4|i[2] {} } { 0.000ns 0.811ns } { 0.000ns 0.738ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[2] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { fqset ladder:u4|i[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { fqset {} fqset~out0 {} ladder:u4|i[3] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ladder:u4|i[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { ladder:u4|i[2] {} } {  } {  } "" } } { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "funset register register setfun:u5\|j\[1\] setfun:u5\|j\[1\] 275.03 MHz Internal " "Info: Clock \"funset\" Internal fmax is restricted to 275.03 MHz between source register \"setfun:u5\|j\[1\]\" and destination register \"setfun:u5\|j\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.025 ns + Longest register register " "Info: + Longest register to register delay is 1.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns setfun:u5\|j\[1\] 1 REG LC_X22_Y17_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y17_N2; Fanout = 11; REG Node = 'setfun:u5\|j\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { setfun:u5|j[1] } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.547 ns) + CELL(0.478 ns) 1.025 ns setfun:u5\|j\[1\] 2 REG LC_X22_Y17_N2 11 " "Info: 2: + IC(0.547 ns) + CELL(0.478 ns) = 1.025 ns; Loc. = LC_X22_Y17_N2; Fanout = 11; REG Node = 'setfun:u5\|j\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.025 ns" { setfun:u5|j[1] setfun:u5|j[1] } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 46.63 % ) " "Info: Total cell delay = 0.478 ns ( 46.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.547 ns ( 53.37 % ) " "Info: Total interconnect delay = 0.547 ns ( 53.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.025 ns" { setfun:u5|j[1] setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.025 ns" { setfun:u5|j[1] {} setfun:u5|j[1] {} } { 0.000ns 0.547ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "funset destination 3.246 ns + Shortest register " "Info: + Shortest clock path from clock \"funset\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns funset 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'funset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { funset } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns setfun:u5\|j\[1\] 2 REG LC_X22_Y17_N2 11 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X22_Y17_N2; Fanout = 11; REG Node = 'setfun:u5\|j\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "funset source 3.246 ns - Longest register " "Info: - Longest clock path from clock \"funset\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns funset 1 CLK PIN_153 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'funset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { funset } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns setfun:u5\|j\[1\] 2 REG LC_X22_Y17_N2 11 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X22_Y17_N2; Fanout = 11; REG Node = 'setfun:u5\|j\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.025 ns" { setfun:u5|j[1] setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.025 ns" { setfun:u5|j[1] {} setfun:u5|j[1] {} } { 0.000ns 0.547ns } { 0.000ns 0.478ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { funset setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { funset {} funset~out0 {} setfun:u5|j[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { setfun:u5|j[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { setfun:u5|j[1] {} } {  } {  } "" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk update\[2\] square:u3\|Q1\[2\] 19.218 ns register " "Info: tco from clock \"clk\" to destination pin \"update\[2\]\" through register \"square:u3\|Q1\[2\]\" is 19.218 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.923 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.935 ns) 3.402 ns square:u3\|qq 2 REG LC_X41_Y13_N1 4 " "Info: 2: + IC(0.998 ns) + CELL(0.935 ns) = 3.402 ns; Loc. = LC_X41_Y13_N1; Fanout = 4; REG Node = 'square:u3\|qq'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.933 ns" { clk square:u3|qq } "NODE_NAME" } } { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.810 ns) + CELL(0.711 ns) 10.923 ns square:u3\|Q1\[2\] 3 REG LC_X21_Y17_N6 9 " "Info: 3: + IC(6.810 ns) + CELL(0.711 ns) = 10.923 ns; Loc. = LC_X21_Y17_N6; Fanout = 9; REG Node = 'square:u3\|Q1\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.521 ns" { square:u3|qq square:u3|Q1[2] } "NODE_NAME" } } { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 28.52 % ) " "Info: Total cell delay = 3.115 ns ( 28.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.808 ns ( 71.48 % ) " "Info: Total interconnect delay = 7.808 ns ( 71.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.923 ns" { clk square:u3|qq square:u3|Q1[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.923 ns" { clk {} clk~out0 {} square:u3|qq {} square:u3|Q1[2] {} } { 0.000ns 0.000ns 0.998ns 6.810ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.071 ns + Longest register pin " "Info: + Longest register to pin delay is 8.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns square:u3\|Q1\[2\] 1 REG LC_X21_Y17_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y17_N6; Fanout = 9; REG Node = 'square:u3\|Q1\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { square:u3|Q1[2] } "NODE_NAME" } } { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.590 ns) 2.372 ns setfun:u5\|Mux5~89 2 COMB LC_X17_Y18_N9 1 " "Info: 2: + IC(1.782 ns) + CELL(0.590 ns) = 2.372 ns; Loc. = LC_X17_Y18_N9; Fanout = 1; COMB Node = 'setfun:u5\|Mux5~89'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.372 ns" { square:u3|Q1[2] setfun:u5|Mux5~89 } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.292 ns) 3.101 ns setfun:u5\|Mux5~90 3 COMB LC_X17_Y18_N2 1 " "Info: 3: + IC(0.437 ns) + CELL(0.292 ns) = 3.101 ns; Loc. = LC_X17_Y18_N2; Fanout = 1; COMB Node = 'setfun:u5\|Mux5~90'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { setfun:u5|Mux5~89 setfun:u5|Mux5~90 } "NODE_NAME" } } { "setfun.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/setfun.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.846 ns) + CELL(2.124 ns) 8.071 ns update\[2\] 4 PIN PIN_20 0 " "Info: 4: + IC(2.846 ns) + CELL(2.124 ns) = 8.071 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'update\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.970 ns" { setfun:u5|Mux5~90 update[2] } "NODE_NAME" } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.006 ns ( 37.24 % ) " "Info: Total cell delay = 3.006 ns ( 37.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.065 ns ( 62.76 % ) " "Info: Total interconnect delay = 5.065 ns ( 62.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.071 ns" { square:u3|Q1[2] setfun:u5|Mux5~89 setfun:u5|Mux5~90 update[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.071 ns" { square:u3|Q1[2] {} setfun:u5|Mux5~89 {} setfun:u5|Mux5~90 {} update[2] {} } { 0.000ns 1.782ns 0.437ns 2.846ns } { 0.000ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.923 ns" { clk square:u3|qq square:u3|Q1[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.923 ns" { clk {} clk~out0 {} square:u3|qq {} square:u3|Q1[2] {} } { 0.000ns 0.000ns 0.998ns 6.810ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.071 ns" { square:u3|Q1[2] setfun:u5|Mux5~89 setfun:u5|Mux5~90 update[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.071 ns" { square:u3|Q1[2] {} setfun:u5|Mux5~89 {} setfun:u5|Mux5~90 {} update[2] {} } { 0.000ns 1.782ns 0.437ns 2.846ns } { 0.000ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}