eda.fit.qmsg

能够产生方波、三角波、正弦波、及阶梯波

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 05 19:29:18 2009 " "Info: Processing started: Mon Jan 05 19:29:18 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off EDA -c EDA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off EDA -c EDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "EDA EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"EDA\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[0\] " "Info: Pin update\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[0] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[1\] " "Info: Pin update\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[1] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[2\] " "Info: Pin update\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[2] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[3\] " "Info: Pin update\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[3] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[4\] " "Info: Pin update\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[4] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[5\] " "Info: Pin update\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[5] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[6\] " "Info: Pin update\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[6] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "update\[7\] " "Info: Pin update\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { update[7] } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { update[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "funset " "Info: Pin funset not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { funset } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 4 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { funset } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { clk } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fqset " "Info: Pin fqset not assigned to an exact location on the device" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { fqset } } } { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fqset } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fqset Global clock in PIN 28 " "Info: Automatically promoted signal \"fqset\" to use Global clock in PIN 28" {  } { { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 5 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "funset Global clock in PIN 153 " "Info: Automatically promoted signal \"funset\" to use Global clock in PIN 153" {  } { { "EDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/EDA.vhd" 4 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sin:u1\|qq Global clock " "Info: Automatically promoted some destinations of signal \"sin:u1\|qq\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin:u1\|qq " "Info: Destination \"sin:u1\|qq\" may be non-global or may not use global clock" {  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0}  } { { "sin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/sin.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "delta:u2\|qq Global clock " "Info: Automatically promoted some destinations of signal \"delta:u2\|qq\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "delta:u2\|qq " "Info: Destination \"delta:u2\|qq\" may be non-global or may not use global clock" {  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0}  } { { "delta.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/delta.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "ladder:u4\|qq Global clock " "Info: Automatically promoted some destinations of signal \"ladder:u4\|qq\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ladder:u4\|qq " "Info: Destination \"ladder:u4\|qq\" may be non-global or may not use global clock" {  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0}  } { { "ladder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/ladder.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "square:u3\|qq Global clock " "Info: Automatically promoted some destinations of signal \"square:u3\|qq\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "square:u3\|qq " "Info: Destination \"square:u3\|qq\" may be non-global or may not use global clock" {  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 24 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0}  } { { "square.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/square.vhd" 24 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}