eda.fit.rpt

能够产生方波、三角波、正弦波、及阶梯波

; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 121     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/桌面/EDA/EDA.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 104 / 12,060 ( < 1 % ) ;
;     -- Combinational with no register       ; 58                     ;
;     -- Register only                        ; 0                      ;
;     -- Combinational with a register        ; 46                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 60                     ;
;     -- 3 input functions                    ; 18                     ;
;     -- 2 input functions                    ; 15                     ;
;     -- 1 input functions                    ; 11                     ;
;     -- 0 input functions                    ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 88                     ;
;     -- arithmetic mode                      ; 16                     ;
;     -- qfbk mode                            ; 6                      ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 19                     ;
;     -- asynchronous clear/load mode         ; 0                      ;
;                                             ;                        ;
; Total registers                             ; 46 / 12,567 ( < 1 % )  ;
; Total LABs                                  ; 13 / 1,206 ( 1 % )     ;
; Logic elements in carry chains              ; 19                     ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 11 / 173 ( 6 % )       ;
;     -- Clock pins                           ; 2 / 2 ( 100 % )        ;
; Global signals                              ; 7                      ;
; M4Ks                                        ; 0 / 52 ( 0 % )         ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )    ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )    ;
; PLLs                                        ; 0 / 2 ( 0 % )          ;
; Global clocks                               ; 7 / 8 ( 88 % )         ;
; JTAGs                                       ; 0 / 1 ( 0 % )          ;
; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%           ;
; Peak interconnect usage (total/H/V)         ; 0% / 1% / 0%           ;
; Maximum fan-out node                        ; sin:u1|tmp[0]          ;
; Maximum fan-out                             ; 24                     ;
; Highest non-global fan-out signal           ; sin:u1|tmp[0]          ;
; Highest non-global fan-out                  ; 23                     ;
; Total fan-out                               ; 415                    ;
; Average fan-out                             ; 3.55                   ;
+---------------------------------------------+------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk    ; 29    ; 1        ; 0            ; 14           ; 0           ; 9                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
; fqset  ; 28    ; 1        ; 0            ; 15           ; 2           ; 4                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
; funset ; 153   ; 3        ; 53           ; 15           ; 1           ; 2                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                  ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load  ;