setfq .vhd.bak

能够产生方波、三角波、正弦波、及阶梯波

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY setfq IS 
	PORT(d,clk:in std_logic;
		         q:out std_logic); 
		END ENTITY setfq;
ARCHITECTURE behave OF setfq IS
	signal i:integer range 0 to 20;
	BEGIN
		process(d,clk)
			begin
			  if d'event and d='1' then
				if i<20 then i<=i+2;
				else i<=0;
				end if;
			   end if;
				
			END PROCESS;
		process(i,clk)
			variable tmp:integer range 0 to 22;
			variable q1:std_logic;
			begin
				if clk'event and clk='1' then
						if tmp<i then tmp:=tmp+1;
							else tmp:=0;q1:=not q1;
						end if;
				end if;
				q<=q1;
			end process;
	END behave;