decim.vhd

Decim流密码ＶＨＤＬ源程序 http://www.ecrypt.eu.org/stream/decimp3.html

--This software is provided 'as-is', without any express or implied warranty.
--In no event will the authors be held liable for any damages arising from the use of this software.

--Permission is granted to anyone to use this software for any purpose,
--excluding commercial applications, and to alter it and redistribute
--it freely except for commercial applications. 

--File:         decim.vhd
--Author:       Richard Stern ([e-mail])
--Organization: Polytechnic University
--------------------------------------------------------
--Description: Decim encryption algorithm
--------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity decim is
port ( clk, rst : in std_logic;
       key      : in std_logic_vector(79 downto 0);
       IV       : in std_logic_vector(63 downto 0);
       key_vld  : in std_logic;
       z        : out std_logic;
       o_vld    : out std_logic);
end entity;

architecture do_it of decim is
type statetype is (IDLE, KEY_INITIALIZE, RUN);
type statetype2 is (IDLE, ABSG_GetZ, ABSG_RUN_DECIMATION);
signal absgstate : statetype2;
signal state   : statetype;
signal x       : std_logic_vector(191 downto 0);
signal x_192   : std_logic;
signal y_xor, y_absg   : std_logic;
signal y_add   : std_logic_vector(7 downto 0);
signal y, e, zj: std_logic;
signal cnt     : integer;
signal absg_s  : std_logic;
signal y_0, y_1: std_logic;
signal o_vld_reg, z_reg : std_logic;

begin

   --LFSR feedback polynomial
   x_192 <= x(0) xor x(3) xor x(4) xor x(23) xor x(36) xor x(37) xor x(60)
             xor x(61) xor x(98) xor x(115) xor x(146) xor x(175) xor x(176)
             xor x(187);
   
   --f filter
   y_xor <= x(1) xor x(13) xor x(28) xor x(45) xor x(54) xor x(65) xor x(104)
             xor x(111) xor x(144) xor x(162) xor x(172) xor x(178) xor x(186)
             xor x(191);
      
   y_add <= ("0000000" & x(13)) + ("0000000" & x(28)) + ("0000000" & x(45)) +
               ("0000000" & x(54)) + ("0000000" & x(65)) + ("0000000" & x(104)) +
               ("0000000" & x(111)) + ("0000000" & x(144)) + ("0000000" & x(162)) +
               ("0000000" & x(172)) + ("0000000" & x(178)) + ("0000000" & x(186)) +
               ("0000000" & x(191));
              
   y <= y_add(1) xor y_xor xor x(1);
   
   --absg input
   y_absg <= y_add(1) xor y_xor;
   
   --output to buffer
   o_vld <= o_vld_reg;
   z <= z_reg;

--y registers
process(clk, rst)
begin
if (rst = '1') then
 y_0 <= '0';
 y_1 <= '0';   
elsif(clk'event and clk = '1') then
 y_0 <= y_absg;
 y_1 <= y_0;
end if;
end process;
 
--ABSG
process(clk, rst)
begin
if (rst = '1') then
absgstate <= IDLE;
z_reg <= '0';
o_vld_reg <= '0';
elsif(clk'event and clk = '1') then
    o_vld_reg <= '0';
    case absgstate is
        when IDLE =>
            if (state = RUN) then
                absgstate <= ABSG_GetZ;
                e <= y_absg;
            end if;
        
        	   when ABSG_GetZ =>
        	   
        	   	z_reg<= y_absg;
        	   	absgstate <= ABSG_RUN_DECIMATION;

        	   when ABSG_RUN_DECIMATION =>
        	   
        	   	if (e = z_reg) then	 --Check if the next value is the 
        	   		o_vld_reg <= '1';
        	   		absgstate <= ABSG_GetZ;
                			e <= y_absg;	
        	   	elsif (e = y_absg) then	  --If the next value is not e then continue the decimation
        	   		absgstate <= IDLE;
        	   		o_vld_reg <= '1';
        	   	end if;
        	   
        	   
        	   when OTHERS =>
                   
        
    end case;
    
end if;
    
end process;

--x register
process(clk, rst)
begin
if (rst = '1') then
   x <= (OTHERS => '0');
elsif (clk'event and clk = '1') then
   if (state = IDLE) then
       x(79 downto 0) <= key;
       x(143 downto 80) <= key(63 downto 0) xor IV;
       x(159 downto 144) <= key(79 downto 64) xor IV(15 downto 0) xor IV(31 downto 16) 
                               xor IV(47 downto 32) xor IV(63 downto 48);
       x(191 downto 160) <= IV(31 downto 0) xor IV(63 downto 32) xor X"FFFFFFFF";
   elsif (state = KEY_INITIALIZE) then
       x(190 downto 0) <= x(191 downto 1);
       x(191) <= x_192 xor y;
   elsif (state = RUN) then
       x(190 downto 0) <= x(191 downto 1);
       x(191) <= x_192;
   end if; 
end if;
end process;

--state machine
process(clk, rst)
begin
if (rst = '1') then
    state <= IDLE;
    cnt <= 1;
    absg_s <= '0';
elsif (clk'event and clk='1') then
    case state is
        when IDLE =>
           if (key_vld = '1') then
             state <= KEY_INITIALIZE;
           end if;
           cnt <= 1;
            
        when KEY_INITIALIZE =>
            if (cnt = 768) then
                state <= RUN;
            else
                cnt <= cnt + 1;
            end if;
        
        when RUN =>

        when OTHERS =>
     end case;


end if;
end process;


end do_it;