步进电机及伺服电机的控制.txt

本程序采用vhdl语言对步进电机及伺服电机进行控制

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ztsdpwm is
    Port (clk,key:in std_logic;--系统时钟/换向按键
    	y,yf:out std_logic;  --正转/反转输出
		yin:in std_logic );  --脉冲输入
end ztsdpwm;

architecture Behavioral of ztsdpwm is
signal y2,y1,yf1:std_logic;
begin

process(key,clk) --换向延时秒脉冲产生模块
variable cnt:integer range 0 to 32000000;
begin
	if key='1' then cnt:=0;
	else if rising_edge(clk) then 
			if cnt<32000000 then cnt:=cnt+1;y2<='0';
			else cnt:=32000000;y2<='1';
			end if;
		end if;
	end if;	
end process;

process(key,yin,y2) 
variable cnt:std_logic:='0';
begin
	if rising_edge(key) then 
	cnt:=not cnt;
	end if;
	case cnt is
	when  '0'=>y<=yin and y2;yf<='0';
	when  '1'=>y<='0';yf<=yin and y2;
	when others=>y<='0';yf<='0';
	end case;
	end process;

end Behavioral;

--/*ANJIAN.VHD*/--按键控制模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity anjian is
    Port (clk,add,sub,rst:in std_logic; --系统时钟/加键/减键/复位
    	 con:out std_logic_vector(6 downto 0) );--占空比计数结果输出
end anjian;

architecture Behavioral of anjian is
signal clkk:std_logic;
begin

process(clk,rst)  --按键检测脉冲产生模块
variable cnt:integer range 0 to 1499999;
begin
	if rst='0' then 
	clkk<='0';cnt:=0;
	elsif clk'event and clk='1' then 
		if cnt>=1499999	then clkk<=not clkk;cnt:=0;
		else cnt:=cnt+1;
		end if;
		end if;
end process;

process(clkk,add,sub,rst)  --占空比调节按键处理模块
variable con1:std_logic_vector(6 downto 0);
begin
	if rst='0' then con1:="0000000";
	elsif clkk'event and clkk='1' then 
		if add='0' then 
		if con1<=99 then 
		con1:=con1+1;
		end if;
		elsif sub='0' then 
		if con1>=1 then 
		con1:=con1-1;
		end if;
		end if;
		end if;
con<=con1;
end process;	

end Behavioral;

--/*PWM.VHD*/--PWM波形产生模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm is
    Port (clk,rst:in std_logic;              --系统时钟/复位
    	con:in std_logic_vector(6 downto 0); --占空比
    	y:out std_logic );                 --PWM脉冲输出
end pwm;

architecture Behavioral of pwm is
signal clkk:std_logic:='0';
begin

process(clk)  
variable cnt:integer range 1 to 100;
begin
	if clk'event and clk='1' then 
		if cnt>=100 then clkk<=not clkk;cnt:=1;
		else cnt:=cnt+1;
		end if;
	end if;
end process;

process(clkk,rst)
variable cnt:std_logic_vector(6 downto 0);
begin
if rst='0' then cnt:="0000000";y<='1';
	elsif clkk'event and clkk='1' then 		
		if cnt<100 then cnt:=cnt+1;
		else	cnt:="0000000";
		end if;
		if cnt>=con then y<='0';
		else y<='1';
		end if;
		end if;
end process;
end Behavioral;

--/*DISP.VHD*/--占空比计数模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity disp is
    Port (con:in std_logic_vector(6 downto 0);  --占空比输入
    	clk:in std_logic;                   --系统时钟
		data_led:out std_logic_vector(7 downto 0); --七段数码管
		shift:out std_logic_vector(3 downto 0) );   --数码管位选信号
end disp;

architecture Behavioral of disp is
signal d1,d2:std_logic_vector(11 downto 0);
signal clkk:std_logic:='0';
signal data_ledin:std_logic_vector(3 downto 0);
begin

process(clk)  --位选扫描信号产生模块
variable cnt:integer range 0 to 79999:=0;
begin
	if rising_edge(clk) then 
	if cnt=79999 then clkk<=not clkk;cnt:=0;
	else cnt:=cnt+1;
	end if;
	end if;
end process;

process(clk)  --计数
begin
	if rising_edge(clk) then 		
	if d1(3 downto 0)<9 then d1(3 downto 0)<=d1(3 downto 0)+1;
	else d1(3 downto 0)<="0000";
		if d1(7 downto 4)<9 then d1(7 downto 4)<=d1(7 downto 4)+1;
	     else d1(7 downto 4)<="0000";
			if d1(11 downto 8)<2 then d1(11 downto 8)<=d1(11 downto 8)+1;
			else d1(11 downto 8)<="0000";
			end if;
		end if;
	end if;
	if conv_integer(d1(11 downto 8))*100+conv_integer(d1(7 downto 4))*10+conv_integer(d1(3 downto 0))=conv_integer(con) then 
	d2<=d1;
	end if;
	end if;
end process;

process(clkk)  --位选信号
variable cnt:std_logic_vector(1 downto 0):="00";
begin
	if rising_edge(clkk) then 
	case cnt is
		when "00"=>shift<="0111";
				 data_ledin<="1111";
				 cnt:=cnt+1;
		when "01"=>shift<="1011";
				 data_ledin<=d2(11 downto 8);
				 cnt:=cnt+1;
		when "10"=>shift<="1101";
				 data_ledin<=d2(7 downto 4);
				 cnt:=cnt+1;
		when "11"=>shift<="1110";
				 data_ledin<=d2(3 downto 0);
				 cnt:="00";
		when others=>cnt:="00";
				   shift<="1111";
		end case;
		end if;
end process;

process (data_ledin)               --译码
  begin
     case data_ledin is
         when"0000"=>data_led<="11000000";--0
	      when"0001"=>data_led<="11111001";--1
			when"0010"=>data_led<="10100100";--2
			when"0011"=>data_led<="10110000";--3
			when"0100"=>data_led<="10011001";--4
			when"0101"=>data_led<="10010010";--5
			when"0110"=>data_led<="10000010";--6
			when"0111"=>data_led<="11111000";--7
			when"1000"=>data_led<="10000000";--8
			when"1001"=>data_led<="10010000";--9
			when others=>data_led<="11111111";--No signal; 
       end case;

end process;

end Behavioral;

--/*ANJIANQD.VHD*/--按键去抖模块
(同下,略去)

------------------------------------------------------------------------------------------------------------------------------------------------------------------------顶层模块--------------------------------------------------------
--/*ANJIANQD.VHD*/--按键去抖模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity anjianqd is
    Port (clk,key:in std_logic;--系统时钟/输入按键
    	keyo:out std_logic );--输出按键
end anjianqd;

architecture Behavioral of anjianqd is
signal clkk,dly,ndly,diff:std_logic;
begin
process(clk)
variable cnt:integer range 1 to 256000;
begin
	if clk'event and clk='1' then 
		if cnt>=2 then cnt:=1; clkk<='1';
		else cnt:=cnt+1;clkk<='0';
		end if;
	end if;
end process;

debunce:block
signal d0,d1,s,r:std_logic;
begin
	process(clk)
	begin
	if clk'event and clk='1' then 
		if clkk='1' then 
		d1<=d0;d0<=key;
		s<=d0 and d1;
		r<=not d0 and not d1;
		end if;
	end if;
	end process;
	dly<=r nor ndly;
	ndly<=s nor dly;
end block;

differetial:block
	signal d1,d0:std_logic;
	begin
	process(clk)
	begin
		if clk'event and clk='1' then 
		d1<=d0;d0<=dly;
		end if;
	end process;
diff<=d0 and not d1;
end block;
keyo<=diff;
end Behavioral;

--/*TOP.VHD*/--顶层控制模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
Port (rst,add,sub,sel,shift1,startstop:in std_logic;
--复位/加键/减键/换向键/步进-伺服切换/起止键
 		 clock:in std_logic;   --系统时钟
		 shift:out std_logic_vector(3 downto 0); --数码管位选信号输出
		 data_led:out std_logic_vector(7 downto 0); --七段数码管输出
		 pwmout:out std_logic_vector(1 downto 0); --伺服电机控制脉冲
		 stepout:out std_logic_vector(3 downto 0) );--步进电机控制脉冲
end top;

architecture Behavioral of top is

component step_top is
    Port (clk,add,sub,sel,rst,startstop:in std_logic;
		step:out std_logic_vector(3 downto 0);
		shift:out std_logic_vector(3 downto 0);
		data_led:out std_logic_vector(7 downto 0) );
end component step_top;

component pwms is
    Port (clk,rst,add,sub,set,startstop:in std_logic;
   		y,yf:out std_logic ;
		shift:out std_logic_vector(3 downto 0);
		data_led:out std_logic_vector(7 downto 0));
end component pwms;

component anjianqd is
    Port (clk,key:in std_logic;
   		keyo:out std_logic );
end component anjianqd;

signal key,addp,subp,selp,rstp,adds,subs,sels,sel1,sel2,rsts:std_logic;
signal startstopp,startstops,q1,q2,q3:std_logic;
signal shift15,rst5,clk:std_logic;
signal shiftp,shifts:std_logic_vector(3 downto 0);
signal data_ledp,data_leds:std_logic_vector(7 downto 0);

begin

process(key,sel2) 
begin
	if rising_edge(key) then 
	sel2<=not sel2;
	end if;
end process;

process(sel1,add,sub,sel,rst5,startstop,shiftp,data_ledp,shifts,data_leds) --按键/显示切换模块
begin
	case sel1 is
	when '1'=>addp<=add;subp<=sub;selp<=sel;rstp<=rst5;startstopp<=startstop;
					adds<='1';subs<='1';sels<='1';rsts<='1';startstops<='1';
					shift<=shiftp;data_led<=data_ledp;
	when '0'=>addp<='1';subp<='1';selp<='1';rstp<='1';startstopp<='1';
					adds<=add;subs<=sub;sels<=sel;rsts<=rst5;startstops<=startstop;
					shift<=shifts;data_led<=data_leds;
	when others=>null;
	end case;
end process;

process(clock)                              --系统初始化模块
variable cnt:integer range 0 to 32000000:=0;
begin
	 if rising_edge(clock) then 
			if    cnt<100000 then cnt:=cnt+1;sel1<='0';rst5<='1';
			elsif cnt<200000 then cnt:=cnt+1;sel1<='0';rst5<='0';
			elsif cnt<300000 then cnt:=cnt+1;sel1<='0';rst5<='1';
			elsif cnt<400000 then cnt:=cnt+1;sel1<='1';rst5<='1';
			elsif cnt<500000 then cnt:=cnt+1;sel1<='1';rst5<='0';
			elsif cnt<600000 then cnt:=cnt+1;sel1<='1';rst5<='1';
			else cnt:=700000;sel1<=sel2;rst5<=rst;
			end if;
	end if;	
end process;
clk<=clock;

u1:anjianqd port map (clk=>clk,key=>shift1,keyo=>key);
u2:step_top port map (clk=>clk,add=>adds,sub=>subs,sel=>sels,step=>stepout,rst=>rsts,
							shift=>shifts,data_led=>data_leds,startstop=>startstops);
u3:pwms port map (clk=>clk,add=>addp,sub=>subp,rst=>rstp,set=>selp,	 
shift=>shiftp,data_led=>data_ledp,y=>pwmout(1),yf=>pwmout(0),startstop=>startstopp);

end Behavioral;