designer.log

静态pll实验程序

Actel Designer Software
Version: 8.4.0.33
Release: v8.4

Created a new design.
'BA_NAME' set to 'PLL_top_ba'
'DESDIR' set to 'D:/Actelprj/Static_PLL/designer/impl1'
'BA_DIR' set to 'D:/Actelprj/Static_PLL/designer/impl1'
'BA_NETLIST_ALSO' set to '1'
'EDNINFLAVOR' set to 'GENERIC'
'NETLIST_NAMING_STYLE' set to 'VERILOG'
'EXPORT_STATUS_REPORT' set to '1'
'EXPORT_STATUS_REPORT_FILENAME' set to 'PLL_top.rpt'
'AUDIT_NETLIST_FILE' set to '1'
'AUDIT_DCF_FILE' set to '1'
'AUDIT_PIN_FILE' set to '1'
'AUDIT_ADL_FILE' set to '1'

 Netlist Reading Time = 0.0 seconds
Imported the files:
   D:\Actelprj\Static_PLL\synthesis\PLL_top.edn
   D:\Actelprj\Static_PLL\synthesis\PLL_top_sdc.sdc

The Import command succeeded ( 00:00:03 )
Design saved to file PLL_top.adb.

The Execute Script command succeeded ( 00:01:27 )
=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : D:\Actelprj\Static_PLL\synthesis\PLL_top.edn
              D:\Actelprj\Static_PLL\synthesis\PLL_top_sdc.sdc
Format      : EDIF
Topcell     : PLL_top
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : No
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

Warning: CMP201: Net u2/Core_GLB drives no load.
Warning: CMP201: Net u2/Core_GLC drives no load.
Warning: CMP201: Net u2/Core_YB drives no load.
Warning: CMP201: Net u2/Core_YC drives no load.

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                1
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        4

    Total macros optimized  5

There were 0 error(s) and 4 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                     Used:     62  Total:  13824   (0.45%)
    IO (W/ clocks)           Used:      5  Total:    119   (4.20%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      1  Total:     18   (5.56%)
    PLL                      Used:      1  Total:      2   (50.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 1      | 6  (16.67%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 41           | 41
    SEQ     | 21           | 21

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 3             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 3      | 0

I/O Placement:

    Locked  :   0
    Placed  :   0
    UnPlaced:   5 ( 100.00% )

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    1       INT_NET       Net   : GLA_c
                          Driver: u2/Core
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    18      CLK_NET       Net   : clk_48M_c
                          Driver: clk_48M_pad
    7       INT_NET       Net   : u1/U1.DWACT_FINC_E[0]
                          Driver: u1/cnt_1_I_16
    6       INT_NET       Net   : u1/U1.DWACT_FINC_E[6]
                          Driver: u1/cnt_1_I_62
    5       INT_NET       Net   : u1/cnt[0]
                          Driver: u1/cnt[0]
    5       INT_NET       Net   : u1/cnt[3]
                          Driver: u1/cnt[3]
    5       INT_NET       Net   : u1/U1.DWACT_FINC_E[7]
                          Driver: u1/cnt_1_I_69
    4       INT_NET       Net   : u1/cnt[1]
                          Driver: u1/cnt[1]
    4       INT_NET       Net   : u1/cnt[8]
                          Driver: u1/cnt[8]
    4       CLK_NET       Net   : u1/cnt[16]
                          Driver: u1/cnt[16]
    4       INT_NET       Net   : u1/cnt[4]
                          Driver: u1/cnt[4]

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    18      CLK_NET       Net   : clk_48M_c
                          Driver: clk_48M_pad
    7       INT_NET       Net   : u1/U1.DWACT_FINC_E[0]
                          Driver: u1/cnt_1_I_16
    6       INT_NET       Net   : u1/U1.DWACT_FINC_E[6]
                          Driver: u1/cnt_1_I_62
    5       INT_NET       Net   : u1/cnt[0]
                          Driver: u1/cnt[0]
    5       INT_NET       Net   : u1/cnt[3]
                          Driver: u1/cnt[3]
    5       INT_NET       Net   : u1/U1.DWACT_FINC_E[7]
                          Driver: u1/cnt_1_I_69
    4       INT_NET       Net   : u1/cnt[1]
                          Driver: u1/cnt[1]
    4       INT_NET       Net   : u1/cnt[8]
                          Driver: u1/cnt[8]
    4       CLK_NET       Net   : u1/cnt[16]
                          Driver: u1/cnt[16]
    4       INT_NET       Net   : u1/cnt[4]
                          Driver: u1/cnt[4]


SDC Import: Begin processing constraints...



SDC Import: End processing constraints


The Compile command succeeded ( 00:00:04 )
Info: I/O Bank Assigner detected (1) out of (5) I/O Bank(s) with locked I/O technologies.

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.
 

Planning global net placement...


Global net placement completed successfully.

                        o - o - o - o - o - o

Timing-driven Placer Started: Mon Nov 24 22:21:36 2008

Placer Finished: Mon Nov 24 22:21:38 2008
Total Placer CPU Time:     00:00:02

                        o - o - o - o - o - o


Timing-driven Router 
Design: PLL_top                         Started: Mon Nov 24 22:21:41 2008

 
Iterative improvement...

Timing-driven Router completed successfully.

Design: PLL_top                         
Finished: Mon Nov 24 22:22:09 2008
Total CPU Time:     00:00:28            Total Elapsed Time: 00:00:28
                        o - o - o - o - o - o

Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.

The Layout command succeeded ( 00:00:38 )

The Export-map command succeeded ( 00:00:19 )
Wrote to the file: D:\Actelprj\Static_PLL\designer\impl1\PLL_top.pdb
CHECKSUM: D43E

The Generate programming file command succeeded ( 00:00:21 )
Design saved to file D:\Actelprj\Static_PLL\designer\impl1\PLL_top.adb.
Design closed.