📄 pll_top.srr
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= Required time: 9.542
- Propagation time: 6.552
= Slack (critical) : 2.990
Number of logic level(s): 4
Starting point: u1.cnt[1] / Q
Ending point: u1.cnt[12] / D
The start point is clocked by PLL_top|clk_48M [rising] on pin CLK
The end point is clocked by PLL_top|clk_48M [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
u1.cnt[1] DFN1 Q Out 0.627 0.627 -
cnt[1] Net - - 1.007 - 4
u1.cnt_1.I_16 AND3 B In - 1.634 -
u1.cnt_1.I_16 AND3 Y Out 0.516 2.150 -
U1\.DWACT_FINC_E[0] Net - - 1.299 - 7
u1.cnt_1.I_62 AND3 A In - 3.449 -
u1.cnt_1.I_62 AND3 Y Out 0.395 3.844 -
U1\.DWACT_FINC_E[6] Net - - 1.211 - 6
u1.cnt_1.I_72 NOR2B B In - 5.055 -
u1.cnt_1.I_72 NOR2B Y Out 0.534 5.589 -
N_22 Net - - 0.274 - 1
u1.cnt_1.I_73 XOR2 A In - 5.862 -
u1.cnt_1.I_73 XOR2 Y Out 0.415 6.278 -
cnt_1[12] Net - - 0.274 - 1
u1.cnt[12] DFN1 D In - 6.552 -
==================================================================================
Total path delay (propagation time + setup) of 7.010 is 2.946(42.0%) logic and 4.064(58.0%) route.
====================================
Detailed Report for Clock: ctrl_PLL|cnt_inferred_clock[16]
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------
u1.dout1 ctrl_PLL|cnt_inferred_clock[16] DFN1 Q dout1 0.627 8.557
u1.dout2 ctrl_PLL|cnt_inferred_clock[16] DFN1 Q dout2 0.627 8.557
=============================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------
u1.dout2 ctrl_PLL|cnt_inferred_clock[16] DFN1 D dout1 9.512 8.557
u1.dout3 ctrl_PLL|cnt_inferred_clock[16] DFN1 D dout2 9.512 8.557
==============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.488
= Required time: 9.512
- Propagation time: 0.955
= Slack (non-critical) : 8.557
Number of logic level(s): 0
Starting point: u1.dout1 / Q
Ending point: u1.dout2 / D
The start point is clocked by ctrl_PLL|cnt_inferred_clock[16] [rising] on pin CLK
The end point is clocked by ctrl_PLL|cnt_inferred_clock[16] [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
u1.dout1 DFN1 Q Out 0.627 0.627 -
dout1 Net - - 0.328 - 2
u1.dout2 DFN1 D In - 0.955 -
=============================================================================
Total path delay (propagation time + setup) of 1.443 is 1.115(77.3%) logic and 0.328(22.7%) route.
====================================
Detailed Report for Clock: ctrl_PLL|key_done_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------
u1.PWN ctrl_PLL|key_done_inferred_clock DFN1 Q POWERDN_c 0.627 7.523
==================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------
u1.PWN ctrl_PLL|key_done_inferred_clock DFN1 D POWERDN_c_i 9.542 7.523
=====================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.458
= Required time: 9.542
- Propagation time: 2.019
= Slack (non-critical) : 7.523
Number of logic level(s): 1
Starting point: u1.PWN / Q
Ending point: u1.PWN / D
The start point is clocked by ctrl_PLL|key_done_inferred_clock [rising] on pin CLK
The end point is clocked by ctrl_PLL|key_done_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
u1.PWN DFN1 Q Out 0.627 0.627 -
POWERDN_c Net - - 0.686 - 3
u1.PWN_RNO INV A In - 1.313 -
u1.PWN_RNO INV Y Out 0.432 1.745 -
POWERDN_c_i Net - - 0.274 - 1
u1.PWN DFN1 D In - 2.019 -
=============================================================================
Total path delay (propagation time + setup) of 2.477 is 1.517(61.2%) logic and 0.960(38.8%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell PLL_top.verilog
Core Cell usage:
cell count area count*area
AND2 4 1.0 4.0
AND3 18 1.0 18.0
GND 3 0.0 0.0
INV 2 1.0 2.0
NOR2B 4 1.0 4.0
NOR3C 1 1.0 1.0
PLL 1 0.0 0.0
PLLINT 1 0.0 0.0
VCC 3 0.0 0.0
XOR2 16 1.0 16.0
DFN1 21 1.0 21.0
----- ----------
TOTAL 74 66.0
IO Cell usage:
cell count
INBUF 2
OUTBUF 3
-----
TOTAL 5
Core Cells : 66 of 13824 (0%)
IO Cells : 5 of 172 (3%)
RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Mon Nov 24 22:06:18 2008
###########################################################]
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