pll_top.srr

静态pll实验程序

#Build: Synplify 9.4A1, Build 169R, Jun 11 2008
#install: D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1
#OS:  6.0
#Hostname: LUAIN-PC

#Implementation: synthesis

#Mon Nov 24 22:06:15 2008

$ Start of Compile
#Mon Nov 24 22:06:15 2008

Synplicity Verilog Compiler, version 1.0, Build 061R, built Jun 30 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v"
@I::"D:\Actelprj\Static_PLL\hdl\ctrl_PLL.v"
@I::"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v"
@I::"D:\Actelprj\Static_PLL\hdl\PLL_top.v"
Verilog syntax check successful!
Selecting top level module PLL_top
@N: CG364 :"D:\Actelprj\Static_PLL\hdl\ctrl_PLL.v":8:7:8:14|Synthesizing module ctrl_PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v":5:7:5:15|Synthesizing module PLL_0P75M

@N: CG364 :"D:\Actelprj\Static_PLL\hdl\PLL_top.v":3:7:3:13|Synthesizing module PLL_top

@W: CS148 :"D:\Actelprj\Static_PLL\hdl\PLL_top.v":25:13:25:14|Undriven input OADIVRST, tying to 0
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 24 22:06:15 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul  2 2008 07:11:59
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.4A1
@N: MF249 |Running in 32-bit mode.

Automatic dissolve at startup in view:work.PLL_top(verilog) of u2(PLL_0P75M)
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB)

@N: MF238 :"d:\actelprj\static_pll\hdl\ctrl_pll.v":28:11:28:21|Found 17 bit incrementor, 'cnt_1[16:0]'
Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 88MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Writing Analyst data base D:\Actelprj\Static_PLL\synthesis\PLL_top.srm
@N: BN225 |Writing default property annotation file D:\Actelprj\Static_PLL\synthesis\PLL_top.map.
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Writing EDIF Netlist and constraint files
Version 9.4A1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

Found clock PLL_top|clk_48M with period 10.00ns 
Found clock ctrl_PLL|key_done_inferred_clock with period 10.00ns 
Found clock ctrl_PLL|cnt_inferred_clock[16] with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 24 22:06:18 2008
#


Top view:               PLL_top
Library name:           fusion
Operating conditions:   COMWC-1 ( T = 70.0, V = 1.42, P = 1.48, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 2.990

                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                       Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------------------------
PLL_top|clk_48M                      100.0 MHz     142.7 MHz     10.000        7.010         2.990     inferred     Inferred_clkgroup_0
ctrl_PLL|cnt_inferred_clock[16]      100.0 MHz     692.9 MHz     10.000        1.443         8.557     inferred     Inferred_clkgroup_1
ctrl_PLL|key_done_inferred_clock     100.0 MHz     403.7 MHz     10.000        2.477         7.523     inferred     Inferred_clkgroup_2
=======================================================================================================================================





Clock Relationships
*******************

Clocks                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                          Ending                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------
PLL_top|clk_48M                   PLL_top|clk_48M                   |  10.000      2.990  |  No paths    -      |  No paths    -      |  No paths    -    
ctrl_PLL|cnt_inferred_clock[16]   ctrl_PLL|cnt_inferred_clock[16]   |  10.000      8.557  |  No paths    -      |  No paths    -      |  No paths    -    
ctrl_PLL|key_done_inferred_clock  ctrl_PLL|key_done_inferred_clock  |  10.000      7.523  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: PLL_top|clk_48M
====================================



Starting Points with Worst Slack
********************************

              Starting                                        Arrival          
Instance      Reference           Type     Pin     Net        Time        Slack
              Clock                                                            
-------------------------------------------------------------------------------
u1.cnt[1]     PLL_top|clk_48M     DFN1     Q       cnt[1]     0.627       2.990
u1.cnt[0]     PLL_top|clk_48M     DFN1     Q       cnt[0]     0.627       3.030
u1.cnt[4]     PLL_top|clk_48M     DFN1     Q       cnt[4]     0.627       3.160
u1.cnt[3]     PLL_top|clk_48M     DFN1     Q       cnt[3]     0.627       3.200
u1.cnt[2]     PLL_top|clk_48M     DFN1     Q       cnt[2]     0.627       3.281
u1.cnt[5]     PLL_top|clk_48M     DFN1     Q       cnt[5]     0.627       3.451
u1.cnt[8]     PLL_top|clk_48M     DFN1     Q       cnt[8]     0.627       3.834
u1.cnt[6]     PLL_top|clk_48M     DFN1     Q       cnt[6]     0.627       3.985
u1.cnt[7]     PLL_top|clk_48M     DFN1     Q       cnt[7]     0.627       4.185
u1.cnt[9]     PLL_top|clk_48M     DFN1     Q       cnt[9]     0.627       4.234
===============================================================================


Ending Points with Worst Slack
******************************

               Starting                                           Required          
Instance       Reference           Type     Pin     Net           Time         Slack
               Clock                                                                
------------------------------------------------------------------------------------
u1.cnt[12]     PLL_top|clk_48M     DFN1     D       cnt_1[12]     9.542        2.990
u1.cnt[11]     PLL_top|clk_48M     DFN1     D       cnt_1[11]     9.542        3.129
u1.cnt[13]     PLL_top|clk_48M     DFN1     D       cnt_1[13]     9.542        3.129
u1.cnt[14]     PLL_top|clk_48M     DFN1     D       cnt_1[14]     9.542        3.129
u1.cnt[15]     PLL_top|clk_48M     DFN1     D       cnt_1[15]     9.542        3.129
u1.cnt[16]     PLL_top|clk_48M     DFN1     D       cnt_1[16]     9.542        3.129
u1.cnt[9]      PLL_top|clk_48M     DFN1     D       cnt_1[9]      9.542        3.873
u1.cnt[10]     PLL_top|clk_48M     DFN1     D       cnt_1[10]     9.542        4.012
u1.cnt[4]      PLL_top|clk_48M     DFN1     D       cnt_1[4]      9.542        4.596
u1.cnt[5]      PLL_top|clk_48M     DFN1     D       cnt_1[5]      9.542        4.735
====================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.458