atmega16.map.rpt

基于FPGA的DDS正弦信号发生器,信号失真小

+--------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                        ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 185                  ;
;     -- Combinational with no register       ; 123                  ;
;     -- Register only                        ; 10                   ;
;     -- Combinational with a register        ; 52                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 85                   ;
;     -- 3 input functions                    ; 35                   ;
;     -- 2 input functions                    ; 48                   ;
;     -- 1 input functions                    ; 7                    ;
;     -- 0 input functions                    ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 136                  ;
;     -- arithmetic mode                      ; 49                   ;
;     -- qfbk mode                            ; 0                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 10                   ;
;     -- asynchronous clear/load mode         ; 0                    ;
;                                             ;                      ;
; Total registers                             ; 62                   ;
; Total logic cells in carry chains           ; 55                   ;
; I/O pins                                    ; 20                   ;
; Maximum fan-out node                        ; dds:inst|dds_add[12] ;
; Maximum fan-out                             ; 34                   ;
; Total fan-out                               ; 662                  ;
; Average fan-out                             ; 3.23                 ;
+---------------------------------------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |atmega16                  ; 185 (0)     ; 62           ; 0          ; 20   ; 0            ; 123 (0)      ; 10 (0)            ; 52 (0)           ; 55 (0)          ; 0 (0)      ; |atmega16           ;
;    |dds:inst|              ; 148 (148)   ; 47           ; 0          ; 0    ; 0            ; 101 (101)    ; 6 (6)             ; 41 (41)          ; 43 (43)         ; 0 (0)      ; |atmega16|dds:inst  ;
;    |tx3:inst1|             ; 37 (37)     ; 15           ; 0          ; 0    ; 0            ; 22 (22)      ; 4 (4)             ; 11 (11)          ; 12 (12)         ; 0 (0)      ; |atmega16|tx3:inst1 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 62    ;
; Number of registers using Synchronous Clear  ; 10    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; dds:inst|dds_m[0]                      ; 5       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |atmega16|dds:inst|dds_m[5] ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |atmega16|tx3:inst1|Mux0    ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |atmega16|tx3:inst1|Mux2    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Nov 06 13:02:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off atmega16 -c atmega16
Info: Found 1 design units, including 1 entities, in source file ../通信3（干活）/atmega16.bdf
    Info: Found entity 1: atmega16
Info: Found 4 design units, including 2 entities, in source file ../通信3（干活）/atmeg16.vhd
    Info: Found design unit 1: tx3-wzy
    Info: Found design unit 2: dds-dac
    Info: Found entity 1: tx3
    Info: Found entity 2: dds
Info: Elaborating entity "atmega16" for the top level hierarchy
Warning: Block or symbol "tx3" of instance "inst1" overlaps another block or symbol
Info: Elaborating entity "dds" for hierarchy "dds:inst"
Info: Elaborating entity "tx3" for hierarchy "tx3:inst1"
Warning (10492): VHDL Process Statement warning at atmeg16.vhd(55): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at atmeg16.vhd(56): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at atmeg16.vhd(57): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at atmeg16.vhd(58): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "cs" stuck at GND
Info: Implemented 205 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 17 output pins
    Info: Implemented 185 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Thu Nov 06 13:02:09 2008
    Info: Elapsed time: 00:00:06