atmega16.fit.rpt

基于FPGA的DDS正弦信号发生器,信号失真小

; Advanced Data - Placement Preparation                                                         ;
+--------------------------------------------------------------------------------+--------------+
; Name                                                                           ; Value        ;
+--------------------------------------------------------------------------------+--------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff           ;
; Mid Wire Use - Fit Attempt 1                                                   ; 34           ;
; Mid Slack - Fit Attempt 1                                                      ; -18184       ;
; Internal Atom Count - Fit Attempt 1                                            ; 180          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 180          ;
; LAB Count - Fit Attempt 1                                                      ; 22           ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.045        ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.227        ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.682        ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:22         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:17;1:5     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:16;1:6     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:16;1:6     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:16;1:6     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:16;1:6     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:21;1:1     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:22         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:17;1:5     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:9;1:11;2:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:9;1:9;2:4  ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:22         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:9;1:13     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:18;1:4     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:21     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:20;1:2     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:22         ;
; LEs in Chains - Fit Attempt 1                                                  ; 55           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 16           ;
; LABs with Chains - Fit Attempt 1                                               ; 7            ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0            ;
; Time - Fit Attempt 1                                                           ; 0            ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016        ;
+--------------------------------------------------------------------------------+--------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Early Slack - Fit Attempt 1         ; -25886 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 14     ;
; Mid Slack - Fit Attempt 1           ; -20038 ;
; Late Wire Use - Fit Attempt 1       ; 15     ;
; Late Slack - Fit Attempt 1          ; -20038 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -18931 ;
; Early Wire Use - Fit Attempt 1      ; 10     ;
; Peak Regional Wire - Fit Attempt 1  ; 9      ;
; Mid Slack - Fit Attempt 1           ; -20175 ;
; Late Slack - Fit Attempt 1          ; -20175 ;
; Late Wire Use - Fit Attempt 1       ; 15     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.186  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Nov 06 13:02:11 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off atmega16 -c atmega16
Info: Selected device EPM240T100C5 for design "atmega16"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "dds:inst|cp_65k" to use Global clock
    Info: Destination "dds:inst|cp_65k" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "dds:inst|cp_1k" to use Global clock
    Info: Destination "dds:inst|cp_1k" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "tx3:inst1|clock" to use Global clock
    Info: Destination "tx3:inst1|clock" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 12.649 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 33; REG Node = 'dds:inst|dds_add[10]'
    Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X7_Y2; Fanout = 2; COMB Node = 'dds:inst|Mux26~359'
    Info: 3: + IC(1.766 ns) + CELL(0.511 ns) = 4.034 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'dds:inst|Mux26~362'
    Info: 4: + IC(2.074 ns) + CELL(0.200 ns) = 6.308 ns; Loc. = LAB_X7_Y2; Fanout = 1; COMB Node = 'dds:inst|Mux26~363'
    Info: 5: + IC(1.537 ns) + CELL(0.740 ns) = 8.585 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'dds:inst|Mux26~365'
    Info: 6: + IC(1.742 ns) + CELL(2.322 ns) = 12.649 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'datap[0]'
    Info: Total cell delay = 3.973 ns ( 31.41 % )
    Info: Total interconnect delay = 8.676 ns ( 68.59 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 9% of the available device resources. Peak interconnect usage is 9%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin cs has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 160 megabytes of memory during processing
    Info: Processing ended: Thu Nov 06 13:02:13 2008
    Info: Elapsed time: 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/王振宇/CPLD/我的程序/dds综合/atmega16.fit.smsg.