i2c_control_top.v.bak

IIC控制器的verilog实现

// File Name: i2c_control.v
//
// Module Description:
// This module implements the I2C slave controller.  This module interprets incoming I2C read and write
// accesses and generates output signals or reads input signals that indicate the type of access that is being performed.

module i2c_control_top(


reset_i,                // global reset
//  I2C bus.
i2c_scl_i,              // I2C master clock.              
i2c_sda,		// 

// The external data signals.
in_reg0,		// Couldn't read name :-}
in_reg1,

out_reg0,
out_reg1,
out_reg2,
out_reg3,
out_reg4,
out_reg5
);



input  reset_i;
input  i2c_scl_i;
inout i2c_sda;


input [7:0] in_reg0;
input [7:0] in_reg1;

output [7:0] out_reg0;
output [7:0] out_reg1;
output [7:0] out_reg2;
output [7:0] out_reg3;
output [7:0] out_reg4;
output [7:0] out_reg5;

wire [7:0] reg_data_i;
wire [7:0] reg_data_o;
wire [2:0] reg_add;

wire [7:0] reg_data_in0;
wire [7:0] reg_data_in1;

wire reg_wr;

// Miscellaineous parameters.
parameter reg_sel0  =   3'h0;
parameter reg_sel1  =   3'h1;
parameter reg_sel2  =   3'h2;
parameter reg_sel3  =   3'h3;
parameter reg_sel4  =   3'h4;
parameter reg_sel5  =   3'h5;
parameter reg_sel6  =   3'h6;
parameter reg_sel7  =   3'h7;

wire mux_sel;

wire i2c_sda_i;
wire i2c_sda_o;
wire sda_oe;

// Signal assignment
//assign mux_sel = (reg_add == reg_sel1) ? 1 : 0;

assign reg_data_i = (reg_add == reg_sel1) ? reg_data_in1 : reg_data_in0;

assign i2c_sda = sda_oe ? i2c_sda_o : 1'bZ;
assign i2c_sda_i = i2c_sda;




// instantiate I2C controller
i2c_control I2C (.reset_i(reset_i),      
		.i2c_scl_i(i2c_scl_i),      
		.i2c_sda_i(i2c_sda_i),   
		.i2c_sda_o(i2c_sda_o),
		.i2c_sda_oe(sda_oe),              
		.reg_add_o(reg_add),          
		.reg_data_i(reg_data_i),        
		.reg_data_o(reg_data_o),         
		.reg_wr_o(reg_wr)            
		);


// instantiate registers

IO_reg  IU1(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(8'h00),         	
		.reg_data_o(reg_data_in0),		
		.reg_data_pin(in_reg0),		
		.reg_add_match(reg_sel0),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b1),		// only inputs
		.reg_dir_in(1'b1)		
		);
IO_reg  IU2(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(8'h00),         	
		.reg_data_o(reg_data_in1),		
		.reg_data_pin(in_reg1),		
		.reg_add_match(reg_sel1),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b1),		// only inputs
		.reg_dir_in(1'b1)		
		);
// outputs
IO_reg  OU1(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg0),		
		.reg_add_match(reg_sel2),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);
		
IO_reg  OU2(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg1),		
		.reg_add_match(reg_sel3),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);

IO_reg  OU3(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg2),		
		.reg_add_match(reg_sel4),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);


IO_reg  OU4(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg3),		
		.reg_add_match(reg_sel5),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);

IO_reg  OU5(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg4),		
		.reg_add_match(reg_sel6),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);
		
IO_reg  OU6(	.reset_i(reset_i),             
		.clk(i2c_scl_i),         
		.reg_add_i(reg_add),        
		.reg_data_i(reg_data_o),         	
		.reg_data_o(),		
		.reg_data_pin(out_reg5),		
		.reg_add_match(reg_sel7),         
		.reg_wr_i(reg_wr),            
		.reg_dir_out_n(1'b0),		//only outputs
		.reg_dir_in(1'b0)		
		);


endmodule