io_reg.v.bak

IIC控制器的verilog实现

// File Name: IO_reg.v
//
// Module Description:
// This module implements the IO registers matched to I2C slave controller.  This module determines the whether
// the IO is an output, input or bidi register. 

module IO_reg(


reset_i,                // global reset



clk,              	// master clock.              

// The external register file control and data signals.
reg_add_i,          	// register file address
reg_data_i,         	// register file write data
reg_data_o,		// register read data back to I2C controller
reg_data_pin,	//input, output, or bidi
reg_add_match,  // register file write data
reg_wr_i,       // register file write strobe
reg_dir_out_n,	// direction of pin 0 = output (If pins are bidis, you can hook up one siganl to both) WR = 0
reg_dir_in		// direction of pin 1 = input 

);

input  clk;
input  reset_i;

input reg_dir_out_n;
input reg_dir_in;
input reg_wr_i;

inout [7:0] reg_data_pin;

input [2:0] reg_add_i;
input [2:0] reg_add_match;
input  [7:0] reg_data_i;
output [7:0] reg_data_o;
reg [7:0] reg_data_o;


// I2C state variables.
reg [7:0] in_reg_int;         	// registered input data from I2C controller ==> pins
wire [7:0] out_reg_int;        	// input data from pin ==> output data to I2C
wire match;               	// address match between add_match and real time address
wire reg_ce;                	// clock enable
wire pin_oe;          		// output enable for output pin data

assign match = (reg_add_i == reg_add_match);
assign reg_ce = (match == 1'b1) && (reg_wr_i == 1'b1);
assign pin_oe = ((~reg_dir_out_n) && (~reg_dir_in));

always @(posedge clk or negedge reset_i)
begin
	if (~reset_i)
	    in_reg_int <= 8'h00;
	else
	    if (reg_ce == 1'b1)
	        in_reg_int <= reg_data_i;
end	 

assign reg_data_pin = pin_oe ? in_reg_int: 8'hZZ;
assign out_reg_int = reg_data_pin;

// reg_data_o will always be clocking on clk so data will be available for a read from I2C

always @(posedge clk or negedge reset_i)
begin
	if (~reset_i)
	    reg_data_o <= 8'h00;
	else
	    reg_data_o <= out_reg_int;
end	 



endmodule