📄 scan_led.rpt
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_X001 = EXP(!cnt100 & !cnt101 & !cnt102 & !cnt103);
-- Node name is '~1260~1'
-- Equation name is '~1260~1', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ041 $ VCC);
_EQ041 = !_LC059 & !_LC060 & !_LC064 & _X012 & _X018 & _X019 & _X020 &
_X021;
_X012 = EXP(!_LC051 & _LC052);
_X018 = EXP(!cnt102 & !cnt103 & !_LC050 & !_LC051 & _LC058 & scan2);
_X019 = EXP(!cnt100 & cnt101 & !_LC050 & !_LC051 & _LC058);
_X020 = EXP( cnt101 & !cnt102 & !_LC050 & !_LC051 & _LC058);
_X021 = EXP(!cnt100 & !cnt102 & !_LC050 & !_LC051 & _LC058);
-- Node name is '~1263~1'
-- Equation name is '~1263~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ042 $ VCC);
_EQ042 = !_LC059 & !_LC060 & !_LC064 & _X001 & _X012 & _X018 & _X019 &
_X020 & _X021;
_X001 = EXP(!cnt100 & !cnt101 & !cnt102 & !cnt103);
_X012 = EXP(!_LC051 & _LC052);
_X018 = EXP(!cnt102 & !cnt103 & !_LC050 & !_LC051 & _LC058 & scan2);
_X019 = EXP(!cnt100 & cnt101 & !_LC050 & !_LC051 & _LC058);
_X020 = EXP( cnt101 & !cnt102 & !_LC050 & !_LC051 & _LC058);
_X021 = EXP(!cnt100 & !cnt102 & !_LC050 & !_LC051 & _LC058);
-- Node name is '~1263~2'
-- Equation name is '~1263~2', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ043 $ GND);
_EQ043 = !cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC051 & !scan0 &
!scan1 & !scan2
# !cnt100 & !cnt101 & !cnt102 & cnt103 & !_LC050 & !_LC051 & !scan0 &
!scan1 & !scan2
# cnt102 & cnt103 & !_LC050 & !_LC051 & _LC058 & !scan0 & !scan1 &
!scan2
# !cnt102 & !cnt103 & !_LC050 & !_LC051 & _LC058 & !scan0 & !scan1 &
!scan2
# !cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC051 & scan0;
-- Node name is '~1263~3'
-- Equation name is '~1263~3', location is LC060, type is buried.
-- synthesized logic cell
_LC060 = LCELL( _EQ044 $ GND);
_EQ044 = !cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC051 & scan2
# !cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC051 & scan1
# !cnt100 & !cnt101 & !cnt102 & cnt103 & !_LC050 & !_LC051 & scan2
# !cnt100 & !cnt101 & !cnt102 & cnt103 & !_LC050 & !_LC051 & scan1
# !cnt100 & !cnt101 & !cnt102 & cnt103 & !_LC050 & !_LC051 & scan0;
-- Node name is '~1263~4'
-- Equation name is '~1263~4', location is LC064, type is buried.
-- synthesized logic cell
_LC064 = LCELL( _EQ045 $ GND);
_EQ045 = cnt102 & cnt103 & !_LC050 & !_LC051 & _LC058 & scan0
# cnt102 & cnt103 & !_LC050 & !_LC051 & _LC058 & scan2
# cnt102 & cnt103 & !_LC050 & !_LC051 & _LC058 & scan1
# !cnt102 & !cnt103 & !_LC050 & !_LC051 & _LC058 & scan0
# !cnt102 & !cnt103 & !_LC050 & !_LC051 & _LC058 & scan1;
-- Node name is '~1293~1'
-- Equation name is '~1293~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ046 $ _EQ047);
_EQ046 = cnt100 & cnt101 & cnt102 & !cnt103 & !_LC038 & !_LC043 &
!_LC051 & !_LC052 & !scan0 & !scan1 & !scan2 & _X002
# cnt102 & cnt103 & !_LC038 & !_LC043 & !_LC044 & !_LC051 &
!_LC052 & !scan0 & !scan1 & !scan2 & _X002
# !cnt102 & !cnt103 & !_LC038 & !_LC043 & !_LC044 & !_LC051 &
!_LC052 & !scan0 & !scan1 & !scan2 & _X002
# cnt100 & cnt101 & cnt102 & !cnt103 & !_LC038 & !_LC043 &
!_LC051 & !_LC052 & scan2 & _X002;
_X002 = EXP( cnt100 & cnt101 & !cnt102 & !cnt103);
_EQ047 = !_LC038 & !_LC043 & !_LC051 & !_LC052 & _X002;
_X002 = EXP( cnt100 & cnt101 & !cnt102 & !cnt103);
-- Node name is '~1293~2'
-- Equation name is '~1293~2', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ048 $ GND);
_EQ048 = cnt100 & cnt101 & cnt102 & !cnt103 & scan1
# cnt100 & cnt101 & cnt102 & !cnt103 & scan0
# cnt102 & cnt103 & !_LC044 & scan2
# cnt102 & cnt103 & !_LC044 & scan1
# cnt102 & cnt103 & !_LC044 & scan0;
-- Node name is '~1293~3'
-- Equation name is '~1293~3', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ049 $ GND);
_EQ049 = !cnt102 & !cnt103 & !_LC044 & scan2
# !cnt102 & !cnt103 & !_LC044 & scan1
# !cnt102 & !cnt103 & !_LC044 & scan0
# cnt100 & cnt101 & !_LC044
# cnt101 & !cnt102 & !_LC044;
-- Node name is '~1296~1'
-- Equation name is '~1296~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ050 $ VCC);
_EQ050 = !_LC047 & _X001;
_X001 = EXP(!cnt100 & !cnt101 & !cnt102 & !cnt103);
-- Node name is '~1326~1'
-- Equation name is '~1326~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ051 $ _EQ052);
_EQ051 = cnt100 & cnt101 & cnt102 & !cnt103 & !_LC027 & !_LC051 &
!_LC052 & !scan0 & !scan1 & !scan2 & _X002 & _X013 & _X014 &
_X022 & _X023 & _X024
# cnt102 & cnt103 & !_LC027 & !_LC042 & !_LC051 & !_LC052 & !scan0 &
!scan1 & !scan2 & _X002 & _X013 & _X014 & _X022 & _X023 &
_X024
# !cnt102 & !cnt103 & !_LC027 & !_LC042 & !_LC051 & !_LC052 & !scan0 &
!scan1 & !scan2 & _X002 & _X013 & _X014 & _X022 & _X023 &
_X024
# cnt100 & cnt101 & cnt102 & !cnt103 & !_LC027 & !_LC051 &
!_LC052 & scan2 & _X002 & _X013 & _X014 & _X022 & _X023 &
_X024;
_X002 = EXP( cnt100 & cnt101 & !cnt102 & !cnt103);
_X013 = EXP( cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC052 & scan1);
_X014 = EXP( cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC052 & scan0);
_X022 = EXP(!cnt102 & !cnt103 & !_LC042 & !_LC050 & !_LC052 & scan0);
_X023 = EXP( cnt100 & cnt101 & !_LC042 & !_LC050 & !_LC052);
_X024 = EXP( cnt101 & !cnt102 & !_LC042 & !_LC050 & !_LC052);
_EQ052 = !_LC027 & !_LC051 & _X013 & _X014 & _X022 & _X023 & _X024;
_X013 = EXP( cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC052 & scan1);
_X014 = EXP( cnt100 & cnt101 & cnt102 & !cnt103 & !_LC050 & !_LC052 & scan0);
_X022 = EXP(!cnt102 & !cnt103 & !_LC042 & !_LC050 & !_LC052 & scan0);
_X023 = EXP( cnt100 & cnt101 & !_LC042 & !_LC050 & !_LC052);
_X024 = EXP( cnt101 & !cnt102 & !_LC042 & !_LC050 & !_LC052);
-- Node name is '~1326~2'
-- Equation name is '~1326~2', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ053 $ GND);
_EQ053 = cnt102 & cnt103 & !_LC042 & !_LC050 & !_LC052 & scan2
# cnt102 & cnt103 & !_LC042 & !_LC050 & !_LC052 & scan1
# cnt102 & cnt103 & !_LC042 & !_LC050 & !_LC052 & scan0
# !cnt102 & !cnt103 & !_LC042 & !_LC050 & !_LC052 & scan2
# !cnt102 & !cnt103 & !_LC042 & !_LC050 & !_LC052 & scan1;
-- Node name is '~1329~1'
-- Equation name is '~1329~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ054 $ GND);
_EQ054 = _LC026 & _X001;
_X001 = EXP(!cnt100 & !cnt101 & !cnt102 & !cnt103);
-- Node name is '~1359~1'
-- Equation name is '~1359~1', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ055 $ GND);
_EQ055 = cnt102 & cnt103 & _LC028 & !_LC051 & !_LC052 & !scan0 & !scan1 &
!scan2 & _X002
# !cnt102 & !cnt103 & _LC028 & !_LC051 & !_LC052 & !scan0 & !scan1 &
!scan2 & _X002
# cnt102 & cnt103 & _LC028 & !_LC051 & !_LC052 & _X002 & _X003
# !cnt102 & !cnt103 & _LC028 & !_LC051 & !_LC052 & _X002 & _X003
# cnt101 & !cnt102 & _LC028 & !_LC051 & !_LC052 & _X002;
_X002 = EXP( cnt100 & cnt101 & !cnt102 & !cnt103);
_X003 = EXP(!scan0 & !scan1 & !scan2);
-- Node name is '~1362~1'
-- Equation name is '~1362~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ056 $ GND);
_EQ056 = _LC045 & _X001;
_X001 = EXP(!cnt100 & !cnt101 & !cnt102 & !cnt103);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs B, C, D
-- _X002 occurs in LABs A, B, C
-- _X003 occurs in LABs A, C
-- _X012 occurs in LABs B, D
Project Information e:\作业\eda\scan_led.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,339K
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