📄 count10.rpt
字号:
r = Fitter-inserted logic cell
Device-Specific Information: e:\作业\eda\count10\count10.rpt
count10
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+--- LC97 SLC0
| +- LC99 SLC1
| |
| | Other LABs fed by signals
| | that feed LAB 'G'
LC | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC97 -> * * | - - - - - - * * | <-- SLC0
Pin
83 -> - - | - - - - - - - - | <-- CLK
LC113-> - * | - - - - - - * * | <-- w
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\作业\eda\count10\count10.rpt
count10
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------------------- LC114 |LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node1
| +--------------------------- LC116 |LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node3
| | +------------------------- LC115 SLC2
| | | +----------------------- LC118 Y00
| | | | +--------------------- LC120 Y01
| | | | | +------------------- LC117 Y02
| | | | | | +----------------- LC123 Y03
| | | | | | | +--------------- LC125 Y04
| | | | | | | | +------------- LC128 Y05
| | | | | | | | | +----------- LC126 Y06
| | | | | | | | | | +--------- LC119 Q3
| | | | | | | | | | | +------- LC124 Q2
| | | | | | | | | | | | +----- LC122 Q1
| | | | | | | | | | | | | +--- LC121 Q0
| | | | | | | | | | | | | | +- LC113 w
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC114-> - - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node1
LC116-> - - - - - - - - - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node3
LC115-> - - * - - - - - - - - - - - * | - - - - - - - * | <-- SLC2
LC119-> - * - * * * * * * * * - * - - | - - - - - - - * | <-- Q3
LC124-> - * - * * * * * * * * * * - - | - - - - - - - * | <-- Q2
LC122-> * * - * * * * * * * * * * - - | - - - - - - - * | <-- Q1
LC121-> * * - * * * * * * * * * * * - | - - - - - - - * | <-- Q0
LC113-> - - * - - - - - - - - - - - * | - - - - - - * * | <-- w
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
LC97 -> - - * - - - - - - - - - - - * | - - - - - - * * | <-- SLC0
LC99 -> - - * - - - - - - - - - - - * | - - - - - - - * | <-- SLC1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\作业\eda\count10\count10.rpt
count10
** EQUATIONS **
CLK : INPUT;
-- Node name is ':15' = 'Q0'
-- Equation name is 'Q0', location is LC121, type is buried.
Q0 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':14' = 'Q1'
-- Equation name is 'Q1', location is LC122, type is buried.
Q1 = DFFE( _EQ001 $ _LC114, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = _LC114 & Q0 & !Q1 & !Q2 & Q3;
-- Node name is ':13' = 'Q2'
-- Equation name is 'Q2', location is LC124, type is buried.
Q2 = TFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = Q0 & Q1;
-- Node name is ':12' = 'Q3'
-- Equation name is 'Q3', location is LC119, type is buried.
Q3 = DFFE( _EQ003 $ _LC116, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = _LC116 & Q0 & !Q1 & !Q2 & Q3;
-- Node name is 'SLC0' = 'P0'
-- Equation name is 'SLC0', location is LC097, type is output.
SLC0 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SLC1' = 'P1'
-- Equation name is 'SLC1', location is LC099, type is output.
SLC1 = TFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = SLC0 & w
# !SLC0 & !w;
-- Node name is 'SLC2' = 'P2'
-- Equation name is 'SLC2', location is LC115, type is output.
SLC2 = TFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = SLC0 & SLC1 & w
# !SLC0 & !SLC1 & !w;
-- Node name is ':19' = 'w'
-- Equation name is 'w', location is LC113, type is buried.
w = TFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = !SLC0 & SLC1 & SLC2 & w
# SLC0 & !SLC1 & !SLC2 & !w;
-- Node name is 'Y00'
-- Equation name is 'Y00', location is LC118, type is output.
Y00 = LCELL( _EQ007 $ !Q3);
_EQ007 = Q0 & !Q1 & !Q2 & !Q3
# !Q0 & !Q1 & Q2 & !Q3
# !Q1 & !Q2 & Q3;
-- Node name is 'Y01'
-- Equation name is 'Y01', location is LC120, type is output.
Y01 = LCELL( _EQ008 $ !Q3);
_EQ008 = Q0 & !Q1 & Q2 & !Q3
# !Q0 & Q1 & Q2 & !Q3
# !Q1 & !Q2 & Q3;
-- Node name is 'Y02'
-- Equation name is 'Y02', location is LC117, type is output.
Y02 = LCELL( _EQ009 $ !Q3);
_EQ009 = !Q0 & Q1 & !Q2 & !Q3
# !Q1 & !Q2 & Q3;
-- Node name is 'Y03'
-- Equation name is 'Y03', location is LC123, type is output.
Y03 = LCELL( _EQ010 $ !Q3);
_EQ010 = Q0 & Q1 & Q2 & !Q3
# Q0 & !Q1 & !Q2 & !Q3
# !Q0 & !Q1 & Q2 & !Q3
# !Q1 & !Q2 & Q3;
-- Node name is 'Y04'
-- Equation name is 'Y04', location is LC125, type is output.
Y04 = LCELL( _EQ011 $ !Q0);
_EQ011 = !Q0 & Q1 & Q3
# !Q0 & !Q1 & Q2;
-- Node name is 'Y05'
-- Equation name is 'Y05', location is LC128, type is output.
Y05 = LCELL( _EQ012 $ !Q1);
_EQ012 = !Q0 & Q1 & Q2 & !Q3
# Q0 & !Q1 & !Q2 & !Q3
# !Q1 & Q2 & Q3;
-- Node name is 'Y06'
-- Equation name is 'Y06', location is LC126, type is output.
Y06 = LCELL( _EQ013 $ !Q3);
_EQ013 = Q0 & Q1 & Q2 & !Q3
# !Q1 & !Q2;
-- Node name is '|LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC114', type is buried
_LC114 = LCELL( Q1 $ Q0);
-- Node name is '|LPM_ADD_SUB:72|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC116', type is buried
_LC116 = LCELL( Q3 $ _EQ014);
_EQ014 = Q0 & Q1 & Q2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\作业\eda\count10\count10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,117K
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