scan_led.vhd

用vhdl编写的十进制计数器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
entity scan_led is
	port(clk:in std_logic;
	     seg:out std_logic_vector(7 downto 0);
	     scan: out std_logic_vector(2 downto 0));
end;

architecture one of scan_led is
    signal cnt10	:	std_logic_vector(3 downto 0);
    signal data		:	std_logic_vector(3 downto 0);
    signal cnt8     :   std_logic_vector(2 downto 0);
    signal flager   :   std_logic;
begin 
------------------10进制计数器
process(clk)
begin
if (clk'event and clk='1') then 
       if(cnt10="1001") then
              cnt10<="0000";
       else
              cnt10<=cnt10+'1';
       end if;
end if;
end process;
------------------8加减进制计数器
process(cnt8)
begin
 if (cnt8="000") then
  flager<='1';  
 elsif(cnt8="111") then 
  flager<='0';
 end if;
end process;
 --case cnt8 is
  --when "111"=>flager<="000";
  --when "000"=>flager<="001";
  --when others=>null;
 --end case;
--end process;

process(clk)
begin
if (clk'event and clk='1') then
   if (flager='1') then  
     cnt8<=cnt8+'1';
   else
     cnt8<=cnt8-'1';
   end if;
end if;
end process;


------------------数码管地址扫描
process(cnt8)
begin
case cnt8 is
when "000"=>scan<="000";data<=cnt10;
when "001"=>scan<="001";data<=cnt10;
when "010"=>scan<="010";data<=cnt10;
when "011"=>scan<="011";data<=cnt10;
when "100"=>scan<="100";data<=cnt10;
when "101"=>scan<="101";data<=cnt10;
when "110"=>scan<="110";data<=cnt10;
when "111"=>scan<="111";data<=cnt10;
when others=>null;
end case;
end process;
------------------8段译码
process(data)
begin
case data is    --abcdefgh
   when "0000"=>seg<="11111100";
   when "0001"=>seg<="01100000";
   when "0010"=>seg<="11011010";
   when "0011"=>seg<="11110010";
   when "0100"=>seg<="01100110";
   when "0101"=>seg<="10110110";
   when "0110"=>seg<="10111110";
   when "0111"=>seg<="11100000";
   when "1000"=>seg<="11111110";
   when "1001"=>seg<="11110110";
   when others=>null;
end case;
end process;
end;