📄 cy62256vso.tan.rpt
字号:
; N/A ; None ; -2.900 ns ; DATA[6] ; FPGADT[6]~reg0 ; GLBCLK ;
; N/A ; None ; -2.900 ns ; FPGADT[6] ; DATA[6]~reg0 ; GLBCLK ;
; N/A ; None ; -2.900 ns ; DATA[7] ; FPGADT[7]~reg0 ; GLBCLK ;
; N/A ; None ; -2.900 ns ; FPGADT[7] ; DATA[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; DATA[0]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGACS ; FPGADT[0]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; DATA[0]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGAWR ; FPGADT[0]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[7]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[0]~en ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[6]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[5]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[4]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[3]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[2]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[1]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; DATA[0]~reg0 ; GLBCLK ;
; N/A ; None ; -3.500 ns ; FPGARD ; FPGADT[0]~reg0 ; GLBCLK ;
+---------------+-------------+-----------+-----------+----------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Jan 08 18:06:38 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CY62256VSO -c CY62256VSO
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "GLBCLK" is an undefined clock
Info: Clock "GLBCLK" has Internal fmax of 116.28 MHz between source register "DATA[7]~reg0" and destination register "DATA[7]~reg0" (period= 8.6 ns)
Info: + Longest register to register delay is 5.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: 2: + IC(3.000 ns) + CELL(2.200 ns) = 5.200 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: Total cell delay = 2.200 ns ( 42.31 % )
Info: Total interconnect delay = 3.000 ns ( 57.69 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "GLBCLK" to destination register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'
Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: Total cell delay = 2.400 ns ( 100.00 % )
Info: - Longest clock path from clock "GLBCLK" to source register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'
Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: Total cell delay = 2.400 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 2.100 ns
Info: tsu for register "DATA[7]~reg0" (data pin = "FPGACS", clock pin = "GLBCLK") is 6.200 ns
Info: + Longest pin to register delay is 6.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_140; Fanout = 53; PIN Node = 'FPGACS'
Info: 2: + IC(3.600 ns) + CELL(2.200 ns) = 6.500 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: Total cell delay = 2.900 ns ( 44.62 % )
Info: Total interconnect delay = 3.600 ns ( 55.38 % )
Info: + Micro setup delay of destination is 2.100 ns
Info: - Shortest clock path from clock "GLBCLK" to destination register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'
Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA[7]~reg0'
Info: Total cell delay = 2.400 ns ( 100.00 % )
Info: tco from clock "GLBCLK" to destination pin "DATA[0]" through register "DATA[0]~en" is 10.700 ns
Info: + Longest clock path from clock "GLBCLK" to source register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'
Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC6; Fanout = 11; REG Node = 'DATA[0]~en'
Info: Total cell delay = 2.400 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Longest register to pin delay is 7.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 11; REG Node = 'DATA[0]~en'
Info: 2: + IC(3.000 ns) + CELL(4.000 ns) = 7.000 ns; Loc. = PIN_173; Fanout = 0; PIN Node = 'DATA[0]'
Info: Total cell delay = 4.000 ns ( 57.14 % )
Info: Total interconnect delay = 3.000 ns ( 42.86 % )
Info: Longest tpd from source pin "FPGACS" to destination pin "CS" is 8.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_140; Fanout = 53; PIN Node = 'FPGACS'
Info: 2: + IC(3.600 ns) + CELL(2.800 ns) = 7.100 ns; Loc. = LC27; Fanout = 1; COMB Node = 'FPGACS~16'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 8.100 ns; Loc. = PIN_172; Fanout = 0; PIN Node = 'CS'
Info: Total cell delay = 4.500 ns ( 55.56 % )
Info: Total interconnect delay = 3.600 ns ( 44.44 % )
Info: th for register "FPGADT[0]~reg0" (data pin = "DATA[0]", clock pin = "GLBCLK") is -2.900 ns
Info: + Longest clock path from clock "GLBCLK" to destination register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'
Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC9; Fanout = 5; REG Node = 'FPGADT[0]~reg0'
Info: Total cell delay = 2.400 ns ( 100.00 % )
Info: + Micro hold delay of destination is 0.600 ns
Info: - Shortest pin to register delay is 5.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_173; Fanout = 1; PIN Node = 'DATA[0]'
Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = IO1; Fanout = 2; COMB Node = 'DATA[0]~31'
Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 5.900 ns; Loc. = LC9; Fanout = 5; REG Node = 'FPGADT[0]~reg0'
Info: Total cell delay = 2.900 ns ( 49.15 % )
Info: Total interconnect delay = 3.000 ns ( 50.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 110 megabytes of memory during processing
Info: Processing ended: Thu Jan 08 18:06:39 2009
Info: Elapsed time: 00:00:01
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