cy62256vso.map.qmsg

用VHDL编写的CY62256VSO芯片的驱动程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 08 18:06:27 2009 " "Info: Processing started: Thu Jan 08 18:06:27 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CY62256VSO -c CY62256VSO " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CY62256VSO -c CY62256VSO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CY62256VSO.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CY62256VSO.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CY62256VSO-BEHIVIOR " "Info: Found design unit 1: CY62256VSO-BEHIVIOR" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CY62256VSO " "Info: Found entity 1: CY62256VSO" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CY62256VSO " "Info: Elaborating entity \"CY62256VSO\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[1\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[1\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[2\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[2\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[3\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[3\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[4\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[4\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[5\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[5\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[6\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[6\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "FPGADT\[7\]~en FPGADT\[0\]~en " "Info: Duplicate register \"FPGADT\[7\]~en\" merged to single register \"FPGADT\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[1\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[1\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[2\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[2\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[3\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[3\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[4\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[4\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[5\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[5\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[6\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[6\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DATA\[7\]~en DATA\[0\]~en " "Info: Duplicate register \"DATA\[7\]~en\" merged to single register \"DATA\[0\]~en\"" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "GLBCLK " "Info: Promoted clock signal driven by pin \"GLBCLK\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "89 " "Info: Implemented 89 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "36 " "Info: Implemented 36 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "157 " "Info: Allocated 157 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 18:06:30 2009 " "Info: Processing ended: Thu Jan 08 18:06:30 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}