cy62256vso.hier_info

用VHDL编写的CY62256VSO芯片的驱动程序.

|CY62256VSO
GLBCLK => DATA[7]~en.CLK
GLBCLK => DATA[7]~reg0.CLK
GLBCLK => DATA[6]~en.CLK
GLBCLK => DATA[6]~reg0.CLK
GLBCLK => DATA[5]~en.CLK
GLBCLK => DATA[5]~reg0.CLK
GLBCLK => DATA[4]~en.CLK
GLBCLK => DATA[4]~reg0.CLK
GLBCLK => DATA[3]~en.CLK
GLBCLK => DATA[3]~reg0.CLK
GLBCLK => DATA[2]~en.CLK
GLBCLK => DATA[2]~reg0.CLK
GLBCLK => DATA[1]~en.CLK
GLBCLK => DATA[1]~reg0.CLK
GLBCLK => DATA[0]~en.CLK
GLBCLK => DATA[0]~reg0.CLK
GLBCLK => FPGADT[7]~en.CLK
GLBCLK => FPGADT[7]~reg0.CLK
GLBCLK => FPGADT[6]~en.CLK
GLBCLK => FPGADT[6]~reg0.CLK
GLBCLK => FPGADT[5]~en.CLK
GLBCLK => FPGADT[5]~reg0.CLK
GLBCLK => FPGADT[4]~en.CLK
GLBCLK => FPGADT[4]~reg0.CLK
GLBCLK => FPGADT[3]~en.CLK
GLBCLK => FPGADT[3]~reg0.CLK
GLBCLK => FPGADT[2]~en.CLK
GLBCLK => FPGADT[2]~reg0.CLK
GLBCLK => FPGADT[1]~en.CLK
GLBCLK => FPGADT[1]~reg0.CLK
GLBCLK => FPGADT[0]~en.CLK
GLBCLK => FPGADT[0]~reg0.CLK
FPGARD => Mux18.IN9
FPGARD => Mux17.IN9
FPGARD => Mux16.IN9
FPGARD => Mux15.IN9
FPGARD => Mux14.IN9
FPGARD => Mux13.IN9
FPGARD => Mux12.IN9
FPGARD => Mux11.IN9
FPGARD => Mux10.IN9
FPGARD => Mux9.IN9
FPGARD => Mux8.IN9
FPGARD => Mux7.IN9
FPGARD => Mux6.IN9
FPGARD => Mux5.IN9
FPGARD => Mux4.IN9
FPGARD => Mux3.IN9
FPGARD => Mux2.IN9
FPGARD => Mux1.IN9
FPGARD => Mux0.IN9
FPGARD => RD.DATAIN
FPGAWR => Mux18.IN10
FPGAWR => Mux17.IN10
FPGAWR => Mux16.IN10
FPGAWR => Mux15.IN10
FPGAWR => Mux14.IN10
FPGAWR => Mux13.IN10
FPGAWR => Mux12.IN10
FPGAWR => Mux11.IN10
FPGAWR => Mux10.IN10
FPGAWR => Mux9.IN10
FPGAWR => Mux8.IN10
FPGAWR => Mux7.IN10
FPGAWR => Mux6.IN10
FPGAWR => Mux5.IN10
FPGAWR => Mux4.IN10
FPGAWR => Mux3.IN10
FPGAWR => Mux2.IN10
FPGAWR => Mux1.IN10
FPGAWR => Mux0.IN10
FPGAWR => WR.DATAIN
FPGACS => Mux18.IN8
FPGACS => Mux17.IN8
FPGACS => Mux16.IN8
FPGACS => Mux15.IN8
FPGACS => Mux14.IN8
FPGACS => Mux13.IN8
FPGACS => Mux12.IN8
FPGACS => Mux11.IN8
FPGACS => Mux10.IN8
FPGACS => Mux9.IN8
FPGACS => Mux8.IN8
FPGACS => Mux7.IN8
FPGACS => Mux6.IN8
FPGACS => Mux5.IN8
FPGACS => Mux4.IN8
FPGACS => Mux3.IN8
FPGACS => Mux2.IN8
FPGACS => Mux1.IN8
FPGACS => Mux0.IN8
FPGACS => CS.DATAIN
FPGAADDR[0] => ADDROUT[0].DATAIN
FPGAADDR[1] => ADDROUT[1].DATAIN
FPGAADDR[2] => ADDROUT[2].DATAIN
FPGAADDR[3] => ADDROUT[3].DATAIN
FPGAADDR[4] => ADDROUT[4].DATAIN
FPGAADDR[5] => ADDROUT[5].DATAIN
FPGAADDR[6] => ADDROUT[6].DATAIN
FPGAADDR[7] => ADDROUT[7].DATAIN
FPGAADDR[8] => ADDROUT[8].DATAIN
FPGAADDR[9] => ADDROUT[9].DATAIN
FPGAADDR[10] => ADDROUT[10].DATAIN
FPGAADDR[11] => ADDROUT[11].DATAIN
FPGAADDR[12] => ADDROUT[12].DATAIN
FPGAADDR[13] => ADDROUT[13].DATAIN
FPGAADDR[14] => ADDROUT[14].DATAIN
FPGADT[0] <= FPGADT[0]~3
FPGADT[1] <= FPGADT[1]~6
FPGADT[2] <= FPGADT[2]~9
FPGADT[3] <= FPGADT[3]~12
FPGADT[4] <= FPGADT[4]~15
FPGADT[5] <= FPGADT[5]~18
FPGADT[6] <= FPGADT[6]~21
FPGADT[7] <= FPGADT[7]~24
RD <= FPGARD.DB_MAX_OUTPUT_PORT_TYPE
WR <= FPGAWR.DB_MAX_OUTPUT_PORT_TYPE
CS <= FPGACS.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[0] <= FPGAADDR[0].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[1] <= FPGAADDR[1].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[2] <= FPGAADDR[2].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[3] <= FPGAADDR[3].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[4] <= FPGAADDR[4].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[5] <= FPGAADDR[5].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[6] <= FPGAADDR[6].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[7] <= FPGAADDR[7].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[8] <= FPGAADDR[8].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[9] <= FPGAADDR[9].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[10] <= FPGAADDR[10].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[11] <= FPGAADDR[11].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[12] <= FPGAADDR[12].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[13] <= FPGAADDR[13].DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[14] <= FPGAADDR[14].DB_MAX_OUTPUT_PORT_TYPE
DATA[0] <= DATA[0]~2
DATA[1] <= DATA[1]~5
DATA[2] <= DATA[2]~8
DATA[3] <= DATA[3]~11
DATA[4] <= DATA[4]~14
DATA[5] <= DATA[5]~17
DATA[6] <= DATA[6]~20
DATA[7] <= DATA[7]~23