prev_cmp_cy62256vso.qmsg

用VHDL编写的CY62256VSO芯片的驱动程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 08 18:03:24 2009 " "Info: Processing started: Thu Jan 08 18:03:24 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CY62256VSO -c CY62256VSO " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CY62256VSO -c CY62256VSO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CY62256VSO.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CY62256VSO.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CY62256VSO-BEHIVIOR " "Info: Found design unit 1: CY62256VSO-BEHIVIOR" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CY62256VSO " "Info: Found entity 1: CY62256VSO" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CY62256VSO " "Info: Elaborating entity \"CY62256VSO\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_ALREADY_DRIVEN_BY_INPUT" "RD_WR\[2\] FPGACS CY62256VSO.vhd(33) " "Error (10031): Net \"RD_WR\[2\]\" at CY62256VSO.vhd(33) is already driven by input port \"FPGACS\", and cannot be driven by another signal" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 10031 "Net \"%1!s!\" at %3!s! is already driven by input port \"%2!s!\", and cannot be driven by another signal" 0 0 "" 0}
{ "Error" "EVRFX_VDB_OBJ_DECL_HERE" "FPGACS CY62256VSO.vhd(12) " "Error (10032): \"FPGACS\" was declared at CY62256VSO.vhd(12)" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 12 0 0 } }  } 0 10032 "\"%1!s!\" was declared at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_ALREADY_DRIVEN_BY_INPUT" "RD_WR\[1\] FPGARD CY62256VSO.vhd(33) " "Error (10031): Net \"RD_WR\[1\]\" at CY62256VSO.vhd(33) is already driven by input port \"FPGARD\", and cannot be driven by another signal" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 10031 "Net \"%1!s!\" at %3!s! is already driven by input port \"%2!s!\", and cannot be driven by another signal" 0 0 "" 0}
{ "Error" "EVRFX_VDB_OBJ_DECL_HERE" "FPGARD CY62256VSO.vhd(10) " "Error (10032): \"FPGARD\" was declared at CY62256VSO.vhd(10)" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 10 0 0 } }  } 0 10032 "\"%1!s!\" was declared at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_NET_ALREADY_DRIVEN_BY_INPUT" "RD_WR\[0\] FPGAWR CY62256VSO.vhd(33) " "Error (10031): Net \"RD_WR\[0\]\" at CY62256VSO.vhd(33) is already driven by input port \"FPGAWR\", and cannot be driven by another signal" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 10031 "Net \"%1!s!\" at %3!s! is already driven by input port \"%2!s!\", and cannot be driven by another signal" 0 0 "" 0}
{ "Error" "EVRFX_VDB_OBJ_DECL_HERE" "FPGAWR CY62256VSO.vhd(11) " "Error (10032): \"FPGAWR\" was declared at CY62256VSO.vhd(11)" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 11 0 0 } }  } 0 10032 "\"%1!s!\" was declared at %2!s!" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 7 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 08 18:03:26 2009 " "Error: Processing ended: Thu Jan 08 18:03:26 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 7 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}